1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LS1043AQDS_QIXIS_H__ 8*4882a593Smuzhiyun #define __LS1043AQDS_QIXIS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Definitions of QIXIS Registers for LS1043AQDS */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* BRDCFG4[4:7] select EC1 and EC2 as a pair */ 13*4882a593Smuzhiyun #define BRDCFG4_EMISEL_MASK 0xe0 14*4882a593Smuzhiyun #define BRDCFG4_EMISEL_SHIFT 5 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* SYSCLK */ 17*4882a593Smuzhiyun #define QIXIS_SYSCLK_66 0x0 18*4882a593Smuzhiyun #define QIXIS_SYSCLK_83 0x1 19*4882a593Smuzhiyun #define QIXIS_SYSCLK_100 0x2 20*4882a593Smuzhiyun #define QIXIS_SYSCLK_125 0x3 21*4882a593Smuzhiyun #define QIXIS_SYSCLK_133 0x4 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun /* DDRCLK */ 24*4882a593Smuzhiyun #define QIXIS_DDRCLK_66 0x0 25*4882a593Smuzhiyun #define QIXIS_DDRCLK_100 0x1 26*4882a593Smuzhiyun #define QIXIS_DDRCLK_125 0x2 27*4882a593Smuzhiyun #define QIXIS_DDRCLK_133 0x3 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* BRDCFG2 - SD clock*/ 30*4882a593Smuzhiyun #define QIXIS_SDCLK1_100 0x0 31*4882a593Smuzhiyun #define QIXIS_SDCLK1_125 0x1 32*4882a593Smuzhiyun #define QIXIS_SDCLK1_165 0x2 33*4882a593Smuzhiyun #define QIXIS_SDCLK1_100_SP 0x3 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #endif 36