1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <i2c.h>
9*4882a593Smuzhiyun #include <asm/io.h>
10*4882a593Smuzhiyun #include <asm/arch/clock.h>
11*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
12*4882a593Smuzhiyun #ifdef CONFIG_FSL_LS_PPA
13*4882a593Smuzhiyun #include <asm/arch/ppa.h>
14*4882a593Smuzhiyun #endif
15*4882a593Smuzhiyun #include <asm/arch/mmu.h>
16*4882a593Smuzhiyun #include <asm/arch/soc.h>
17*4882a593Smuzhiyun #include <hwconfig.h>
18*4882a593Smuzhiyun #include <environment.h>
19*4882a593Smuzhiyun #include <fsl_mmdc.h>
20*4882a593Smuzhiyun #include <netdev.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
23*4882a593Smuzhiyun
checkboard(void)24*4882a593Smuzhiyun int checkboard(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun puts("Board: LS1012AFRDM ");
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun return 0;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun
dram_init(void)31*4882a593Smuzhiyun int dram_init(void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun static const struct fsl_mmdc_info mparam = {
34*4882a593Smuzhiyun 0x04180000, /* mdctl */
35*4882a593Smuzhiyun 0x00030035, /* mdpdc */
36*4882a593Smuzhiyun 0x12554000, /* mdotc */
37*4882a593Smuzhiyun 0xbabf7954, /* mdcfg0 */
38*4882a593Smuzhiyun 0xdb328f64, /* mdcfg1 */
39*4882a593Smuzhiyun 0x01ff00db, /* mdcfg2 */
40*4882a593Smuzhiyun 0x00001680, /* mdmisc */
41*4882a593Smuzhiyun 0x0f3c8000, /* mdref */
42*4882a593Smuzhiyun 0x00002000, /* mdrwd */
43*4882a593Smuzhiyun 0x00bf1023, /* mdor */
44*4882a593Smuzhiyun 0x0000003f, /* mdasp */
45*4882a593Smuzhiyun 0x0000022a, /* mpodtctrl */
46*4882a593Smuzhiyun 0xa1390003, /* mpzqhwctrl */
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun mmdc_init(&mparam);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
52*4882a593Smuzhiyun #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
53*4882a593Smuzhiyun /* This will break-before-make MMU for DDR */
54*4882a593Smuzhiyun update_early_mmu_table();
55*4882a593Smuzhiyun #endif
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
board_eth_init(bd_t * bis)60*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun return pci_eth_init(bis);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
board_early_init_f(void)65*4882a593Smuzhiyun int board_early_init_f(void)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun fsl_lsch2_early_init_f();
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
board_init(void)72*4882a593Smuzhiyun int board_init(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
75*4882a593Smuzhiyun /*
76*4882a593Smuzhiyun * Set CCI-400 control override register to enable barrier
77*4882a593Smuzhiyun * transaction
78*4882a593Smuzhiyun */
79*4882a593Smuzhiyun out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #ifdef CONFIG_ENV_IS_NOWHERE
82*4882a593Smuzhiyun gd->env_addr = (ulong)&default_environment[0];
83*4882a593Smuzhiyun #endif
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #ifdef CONFIG_FSL_LS_PPA
86*4882a593Smuzhiyun ppa_init();
87*4882a593Smuzhiyun #endif
88*4882a593Smuzhiyun return 0;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
ft_board_setup(void * blob,bd_t * bd)91*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun arch_fixup_fdt(blob);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun ft_cpu_setup(blob, bd);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99