xref: /OK3568_Linux_fs/u-boot/board/freescale/common/zm7300.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:     GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun /* Power-One ZM7300 DPM */
8*4882a593Smuzhiyun #include "zm7300.h"
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #define DPM_WP 0x96
11*4882a593Smuzhiyun #define WRP_OPCODE 0x01
12*4882a593Smuzhiyun #define WRM_OPCODE 0x02
13*4882a593Smuzhiyun #define RRP_OPCODE 0x11
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define DPM_SUCCESS 0x01
16*4882a593Smuzhiyun #define DPM_EXEC_FAIL 0x00
17*4882a593Smuzhiyun 
18*4882a593Smuzhiyun static const uint16_t hex_to_1_10mv[] = {
19*4882a593Smuzhiyun 	5000,
20*4882a593Smuzhiyun 	5125,
21*4882a593Smuzhiyun 	5250,
22*4882a593Smuzhiyun 	5375,
23*4882a593Smuzhiyun 	5500,
24*4882a593Smuzhiyun 	5625,
25*4882a593Smuzhiyun 	5750,
26*4882a593Smuzhiyun 	5875,
27*4882a593Smuzhiyun 	6000,
28*4882a593Smuzhiyun 	6125,
29*4882a593Smuzhiyun 	6250,
30*4882a593Smuzhiyun 	6375,
31*4882a593Smuzhiyun 	6500,
32*4882a593Smuzhiyun 	6625,
33*4882a593Smuzhiyun 	6750,
34*4882a593Smuzhiyun 	6875,
35*4882a593Smuzhiyun 	7000,
36*4882a593Smuzhiyun 	7125,
37*4882a593Smuzhiyun 	7250,
38*4882a593Smuzhiyun 	7375,
39*4882a593Smuzhiyun 	7500,
40*4882a593Smuzhiyun 	7625,
41*4882a593Smuzhiyun 	7750,
42*4882a593Smuzhiyun 	7875,
43*4882a593Smuzhiyun 	8000,
44*4882a593Smuzhiyun 	8125,
45*4882a593Smuzhiyun 	8250,
46*4882a593Smuzhiyun 	8375,
47*4882a593Smuzhiyun 	8500,
48*4882a593Smuzhiyun 	8625,
49*4882a593Smuzhiyun 	8750,
50*4882a593Smuzhiyun 	8875,
51*4882a593Smuzhiyun 	9000,
52*4882a593Smuzhiyun 	9125,
53*4882a593Smuzhiyun 	9250,
54*4882a593Smuzhiyun 	9375,
55*4882a593Smuzhiyun 	9500,  /* 0.95mV */
56*4882a593Smuzhiyun 	9625,
57*4882a593Smuzhiyun 	9750,
58*4882a593Smuzhiyun 	9875,
59*4882a593Smuzhiyun 	10000,  /* 1.0V */
60*4882a593Smuzhiyun 	10125,
61*4882a593Smuzhiyun 	10250,
62*4882a593Smuzhiyun 	10375,
63*4882a593Smuzhiyun 	10500,
64*4882a593Smuzhiyun 	10625,
65*4882a593Smuzhiyun 	10750,
66*4882a593Smuzhiyun 	10875,
67*4882a593Smuzhiyun 	11000,
68*4882a593Smuzhiyun 	11125,
69*4882a593Smuzhiyun 	11250,
70*4882a593Smuzhiyun 	11375,
71*4882a593Smuzhiyun 	11500,
72*4882a593Smuzhiyun 	11625,
73*4882a593Smuzhiyun 	11750,
74*4882a593Smuzhiyun 	11875,
75*4882a593Smuzhiyun 	12000,
76*4882a593Smuzhiyun 	12125,
77*4882a593Smuzhiyun 	12250,
78*4882a593Smuzhiyun 	12375,
79*4882a593Smuzhiyun 	0,	/* reserved */
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun /* Read Data d from Register r of POL p */
dpm_rrp(uchar r)84*4882a593Smuzhiyun u8 dpm_rrp(uchar r)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	u8 ret[5];
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun 	ret[0] = RRP_OPCODE;
89*4882a593Smuzhiyun 	/* POL is 0 */
90*4882a593Smuzhiyun 	ret[1] = 0;
91*4882a593Smuzhiyun 	ret[2] = r;
92*4882a593Smuzhiyun 	i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
93*4882a593Smuzhiyun 	if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
94*4882a593Smuzhiyun 		debug("RRP_OPCODE returned success data is %x\n", ret[0]);
95*4882a593Smuzhiyun 		return ret[0];
96*4882a593Smuzhiyun 	} else {
97*4882a593Smuzhiyun 		return -1;
98*4882a593Smuzhiyun 	}
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun /* Write Data d into DPM register r (RAM) */
dpm_wrm(u8 r,u8 d)102*4882a593Smuzhiyun int dpm_wrm(u8 r, u8 d)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	u8 ret[5];
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	ret[0] = WRM_OPCODE;
107*4882a593Smuzhiyun 	ret[1] = r;
108*4882a593Smuzhiyun 	ret[2] = d;
109*4882a593Smuzhiyun 	i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
110*4882a593Smuzhiyun 	if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
111*4882a593Smuzhiyun 		debug("WRM_OPCODE returned success data is %x\n", ret[0]);
112*4882a593Smuzhiyun 		return ret[0];
113*4882a593Smuzhiyun 	} else {
114*4882a593Smuzhiyun 		return -1;
115*4882a593Smuzhiyun 	}
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun /* Write Data d into Register r of POL(s) a */
dpm_wrp(u8 r,u8 d)119*4882a593Smuzhiyun int dpm_wrp(u8 r, u8 d)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun 	u8 ret[7];
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	ret[0] = WRP_OPCODE;
124*4882a593Smuzhiyun 	/* only POL0 is present */
125*4882a593Smuzhiyun 	ret[1] = 0x01;
126*4882a593Smuzhiyun 	ret[2] = 0x00;
127*4882a593Smuzhiyun 	ret[3] = 0x00;
128*4882a593Smuzhiyun 	ret[4] = 0x00;
129*4882a593Smuzhiyun 	ret[5] = r;
130*4882a593Smuzhiyun 	ret[6] = d;
131*4882a593Smuzhiyun 	i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
132*4882a593Smuzhiyun 	if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
133*4882a593Smuzhiyun 		debug("WRP_OPCODE returned success data is %x\n", ret[0]);
134*4882a593Smuzhiyun 		return 0;
135*4882a593Smuzhiyun 	} else {
136*4882a593Smuzhiyun 		return -1;
137*4882a593Smuzhiyun 	}
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* Uses the DPM command RRP */
zm_read(uchar reg)141*4882a593Smuzhiyun u8 zm_read(uchar reg)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun 	return dpm_rrp(reg);
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun /* ZM_write --
147*4882a593Smuzhiyun 	Steps:
148*4882a593Smuzhiyun 	a. Write data to the register
149*4882a593Smuzhiyun 	b. Read data from register and compare to written value
150*4882a593Smuzhiyun 	c. Return return_code & voltage_read
151*4882a593Smuzhiyun */
zm_write(u8 reg,u8 data)152*4882a593Smuzhiyun u8 zm_write(u8 reg, u8 data)
153*4882a593Smuzhiyun {
154*4882a593Smuzhiyun 	u8 d;
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun 	/* write data to register */
157*4882a593Smuzhiyun 	dpm_wrp(reg, data);
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun 	/* read register and compare to written value */
160*4882a593Smuzhiyun 	d = dpm_rrp(reg);
161*4882a593Smuzhiyun 	if (d != data) {
162*4882a593Smuzhiyun 		printf("zm_write : Comparison register data failed\n");
163*4882a593Smuzhiyun 		return -1;
164*4882a593Smuzhiyun 	}
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	return d;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
169*4882a593Smuzhiyun /* zm_write_out_voltage
170*4882a593Smuzhiyun  * voltage in 1/10 mV
171*4882a593Smuzhiyun  */
zm_write_voltage(int voltage)172*4882a593Smuzhiyun int zm_write_voltage(int voltage)
173*4882a593Smuzhiyun {
174*4882a593Smuzhiyun 	u8 reg = 0x7, vid;
175*4882a593Smuzhiyun 	uint16_t voltage_read;
176*4882a593Smuzhiyun 	u8 ret;
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	vid =  (voltage - 5000) / ZM_STEP;
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	ret = zm_write(reg, vid);
181*4882a593Smuzhiyun 	if (ret != -1) {
182*4882a593Smuzhiyun 		voltage_read = hex_to_1_10mv[ret];
183*4882a593Smuzhiyun 		debug("voltage set to %dmV\n", voltage_read/10);
184*4882a593Smuzhiyun 		return voltage_read;
185*4882a593Smuzhiyun 	}
186*4882a593Smuzhiyun 	return -1;
187*4882a593Smuzhiyun }
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun /* zm_read_out_voltage
190*4882a593Smuzhiyun  * voltage in 1/10 mV
191*4882a593Smuzhiyun  */
zm_read_voltage(void)192*4882a593Smuzhiyun int zm_read_voltage(void)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	u8 reg = 0x7;
195*4882a593Smuzhiyun 	u8 ret;
196*4882a593Smuzhiyun 	int voltage;
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	ret = zm_read(reg);
199*4882a593Smuzhiyun 	if (ret != -1) {
200*4882a593Smuzhiyun 		voltage =  hex_to_1_10mv[ret];
201*4882a593Smuzhiyun 		debug("Voltage read is %dmV\n", voltage/10);
202*4882a593Smuzhiyun 		return voltage;
203*4882a593Smuzhiyun 	} else {
204*4882a593Smuzhiyun 		return -1;
205*4882a593Smuzhiyun 	}
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun 
zm_disable_wp()208*4882a593Smuzhiyun int zm_disable_wp()
209*4882a593Smuzhiyun {
210*4882a593Smuzhiyun 	u8 new_wp_value;
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun 	/* Disable using Write-Protect register 0x96 */
213*4882a593Smuzhiyun 	new_wp_value = 0x8;
214*4882a593Smuzhiyun 	if ((dpm_wrm(DPM_WP, new_wp_value)) < 0) {
215*4882a593Smuzhiyun 		printf("Disable Write-Protect register failed\n");
216*4882a593Smuzhiyun 		return -1;
217*4882a593Smuzhiyun 	}
218*4882a593Smuzhiyun 	return 0;
219*4882a593Smuzhiyun }
220*4882a593Smuzhiyun 
zm_enable_wp()221*4882a593Smuzhiyun int zm_enable_wp()
222*4882a593Smuzhiyun {
223*4882a593Smuzhiyun 	u8 orig_wp_value;
224*4882a593Smuzhiyun 	orig_wp_value = 0x0;
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	/* Enable using Write-Protect register 0x96 */
227*4882a593Smuzhiyun 	if ((dpm_wrm(DPM_WP, orig_wp_value)) < 0) {
228*4882a593Smuzhiyun 		printf("Enable Write-Protect register failed\n");
229*4882a593Smuzhiyun 		return -1;
230*4882a593Smuzhiyun 	}
231*4882a593Smuzhiyun 	return 0;
232*4882a593Smuzhiyun }
233*4882a593Smuzhiyun 
234