1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include "vsc3316_3308.h"
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #define REVISION_ID_REG 0x7E
10*4882a593Smuzhiyun #define INTERFACE_MODE_REG 0x79
11*4882a593Smuzhiyun #define CURRENT_PAGE_REGISTER 0x7F
12*4882a593Smuzhiyun #define CONNECTION_CONFIG_PAGE 0x00
13*4882a593Smuzhiyun #define INPUT_STATE_REG 0x13
14*4882a593Smuzhiyun #define GLOBAL_INPUT_ISE1 0x51
15*4882a593Smuzhiyun #define GLOBAL_INPUT_ISE2 0x52
16*4882a593Smuzhiyun #define GLOBAL_INPUT_GAIN 0x53
17*4882a593Smuzhiyun #define GLOBAL_INPUT_LOS 0x55
18*4882a593Smuzhiyun #define GLOBAL_OUTPUT_PE1 0x56
19*4882a593Smuzhiyun #define GLOBAL_OUTPUT_PE2 0x57
20*4882a593Smuzhiyun #define GLOBAL_OUTPUT_LEVEL 0x58
21*4882a593Smuzhiyun #define GLOBAL_OUTPUT_TERMINATION 0x5A
22*4882a593Smuzhiyun #define GLOBAL_CORE_CNTRL 0x5D
23*4882a593Smuzhiyun #define OUTPUT_MODE_PAGE 0x23
24*4882a593Smuzhiyun #define CORE_CONTROL_PAGE 0x25
25*4882a593Smuzhiyun #define CORE_CONFIG_REG 0x75
26*4882a593Smuzhiyun
vsc_if_enable(unsigned int vsc_addr)27*4882a593Smuzhiyun int vsc_if_enable(unsigned int vsc_addr)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun u8 data;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun debug("VSC:Configuring VSC at I2C address 0x%2x"
32*4882a593Smuzhiyun " for 2-wire interface\n", vsc_addr);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* enable 2-wire Serial InterFace (I2C) */
35*4882a593Smuzhiyun data = 0x02;
36*4882a593Smuzhiyun return i2c_write(vsc_addr, INTERFACE_MODE_REG, 1, &data, 1);
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
vsc3316_config(unsigned int vsc_addr,int8_t con_arr[][2],unsigned int num_con)39*4882a593Smuzhiyun int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
40*4882a593Smuzhiyun unsigned int num_con)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun unsigned int i;
43*4882a593Smuzhiyun u8 rev_id = 0;
44*4882a593Smuzhiyun int ret;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun debug("VSC:Initializing VSC3316 at I2C address 0x%2x"
47*4882a593Smuzhiyun " for Tx\n", vsc_addr);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
50*4882a593Smuzhiyun if (ret < 0) {
51*4882a593Smuzhiyun printf("VSC:0x%x could not read REV_ID from device.\n",
52*4882a593Smuzhiyun vsc_addr);
53*4882a593Smuzhiyun return ret;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun if (rev_id != 0xab) {
57*4882a593Smuzhiyun printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
58*4882a593Smuzhiyun vsc_addr);
59*4882a593Smuzhiyun return -ENODEV;
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun ret = vsc_if_enable(vsc_addr);
63*4882a593Smuzhiyun if (ret) {
64*4882a593Smuzhiyun printf("VSC:0x%x could not configured for 2-wire I/F.\n",
65*4882a593Smuzhiyun vsc_addr);
66*4882a593Smuzhiyun return ret;
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* config connections - page 0x00 */
70*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /* Making crosspoint connections, by connecting required
73*4882a593Smuzhiyun * input to output */
74*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
75*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun /* input state - page 0x13 */
78*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
79*4882a593Smuzhiyun /* Configuring the required input of the switch */
80*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
81*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][0], 0x80);
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* Setting Global Input LOS threshold value */
84*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /* config output mode - page 0x23 */
87*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
88*4882a593Smuzhiyun /* Turn ON the Output driver correspond to required output*/
89*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
90*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][1], 0);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* configure global core control register, Turn on Global core power */
93*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun vsc_wp_config(vsc_addr);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun #ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
vsc3308_config_adjust(unsigned int vsc_addr,const int8_t con_arr[][2],unsigned int num_con)101*4882a593Smuzhiyun int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
102*4882a593Smuzhiyun unsigned int num_con)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun unsigned int i;
105*4882a593Smuzhiyun u8 rev_id = 0;
106*4882a593Smuzhiyun int ret;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
109*4882a593Smuzhiyun vsc_addr);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
112*4882a593Smuzhiyun if (ret < 0) {
113*4882a593Smuzhiyun printf("VSC:0x%x could not read REV_ID from device.\n",
114*4882a593Smuzhiyun vsc_addr);
115*4882a593Smuzhiyun return ret;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if (rev_id != 0xab) {
119*4882a593Smuzhiyun printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
120*4882a593Smuzhiyun vsc_addr);
121*4882a593Smuzhiyun return -ENODEV;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun ret = vsc_if_enable(vsc_addr);
125*4882a593Smuzhiyun if (ret) {
126*4882a593Smuzhiyun printf("VSC:0x%x could not configured for 2-wire I/F.\n",
127*4882a593Smuzhiyun vsc_addr);
128*4882a593Smuzhiyun return ret;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* config connections - page 0x00 */
132*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* Configure Global Input ISE */
135*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0);
136*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* Configure Tx/Rx Global Output PE1 */
139*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun /* Configure Tx/Rx Global Output PE2 */
142*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun /* Configure Tx/Rx Global Input GAIN */
145*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F);
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun /* Setting Global Input LOS threshold value */
148*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun /* Setting Global output termination */
151*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun /* Configure Tx/Rx Global Output level */
154*4882a593Smuzhiyun if (vsc_addr == VSC3308_TX_ADDRESS)
155*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4);
156*4882a593Smuzhiyun else
157*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2);
158*4882a593Smuzhiyun
159*4882a593Smuzhiyun /* Making crosspoint connections, by connecting required
160*4882a593Smuzhiyun * input to output */
161*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
162*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
163*4882a593Smuzhiyun
164*4882a593Smuzhiyun /* input state - page 0x13 */
165*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
166*4882a593Smuzhiyun /* Turning off all the required input of the switch */
167*4882a593Smuzhiyun for (i = 0; i < num_con; i++)
168*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][0], 1);
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* only turn on specific Tx/Rx requested by the XFI erratum */
171*4882a593Smuzhiyun if (vsc_addr == VSC3308_TX_ADDRESS) {
172*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 2, 0);
173*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 3, 0);
174*4882a593Smuzhiyun } else {
175*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 0, 0);
176*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 1, 0);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun /* config output mode - page 0x23 */
180*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
181*4882a593Smuzhiyun /* Turn off the Output driver correspond to required output*/
182*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
183*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][1], 1);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun /* only turn on specific Tx/Rx requested by the XFI erratum */
186*4882a593Smuzhiyun if (vsc_addr == VSC3308_TX_ADDRESS) {
187*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 0, 0);
188*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 1, 0);
189*4882a593Smuzhiyun } else {
190*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 3, 0);
191*4882a593Smuzhiyun i2c_reg_write(vsc_addr, 4, 0);
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun /* configure global core control register, Turn on Global core power */
195*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun vsc_wp_config(vsc_addr);
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun return 0;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun #endif
202*4882a593Smuzhiyun
vsc3308_config(unsigned int vsc_addr,const int8_t con_arr[][2],unsigned int num_con)203*4882a593Smuzhiyun int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
204*4882a593Smuzhiyun unsigned int num_con)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun unsigned int i;
207*4882a593Smuzhiyun u8 rev_id = 0;
208*4882a593Smuzhiyun int ret;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun debug("VSC:Initializing VSC3308 at I2C address 0x%x"
211*4882a593Smuzhiyun " for Tx\n", vsc_addr);
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
214*4882a593Smuzhiyun if (ret < 0) {
215*4882a593Smuzhiyun printf("VSC:0x%x could not read REV_ID from device.\n",
216*4882a593Smuzhiyun vsc_addr);
217*4882a593Smuzhiyun return ret;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun if (rev_id != 0xab) {
221*4882a593Smuzhiyun printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
222*4882a593Smuzhiyun vsc_addr);
223*4882a593Smuzhiyun return -ENODEV;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun ret = vsc_if_enable(vsc_addr);
227*4882a593Smuzhiyun if (ret) {
228*4882a593Smuzhiyun printf("VSC:0x%x could not configured for 2-wire I/F.\n",
229*4882a593Smuzhiyun vsc_addr);
230*4882a593Smuzhiyun return ret;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun /* config connections - page 0x00 */
234*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* Making crosspoint connections, by connecting required
237*4882a593Smuzhiyun * input to output */
238*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
239*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun /*Configure Global Input ISE and gain */
242*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0x12);
243*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0x12);
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun /* input state - page 0x13 */
246*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
247*4882a593Smuzhiyun /* Turning ON the required input of the switch */
248*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
249*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][0], 0);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun /* Setting Global Input LOS threshold value */
252*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0x60);
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun /* config output mode - page 0x23 */
255*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
256*4882a593Smuzhiyun /* Turn ON the Output driver correspond to required output*/
257*4882a593Smuzhiyun for (i = 0; i < num_con ; i++)
258*4882a593Smuzhiyun i2c_reg_write(vsc_addr, con_arr[i][1], 0);
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun /* configure global core control register, Turn on Global core power */
261*4882a593Smuzhiyun i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun vsc_wp_config(vsc_addr);
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun return 0;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun
vsc_wp_config(unsigned int vsc_addr)268*4882a593Smuzhiyun void vsc_wp_config(unsigned int vsc_addr)
269*4882a593Smuzhiyun {
270*4882a593Smuzhiyun debug("VSC:Configuring VSC at address:0x%x for WP\n", vsc_addr);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /* For new crosspoint configuration to occur, WP bit of
273*4882a593Smuzhiyun * CORE_CONFIG_REG should be set 1 and then reset to 0 */
274*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x01);
275*4882a593Smuzhiyun i2c_reg_write(vsc_addr, CORE_CONFIG_REG, 0x0);
276*4882a593Smuzhiyun }
277