1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __VID_H_ 8*4882a593Smuzhiyun #define __VID_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A 11*4882a593Smuzhiyun #define IR36021_LOOP1_VOUT_OFFSET 0x9A 12*4882a593Smuzhiyun #define IR36021_MFR_ID_OFFSET 0x92 13*4882a593Smuzhiyun #define IR36021_MFR_ID 0x43 14*4882a593Smuzhiyun #define IR36021_INTEL_MODE_OOFSET 0x14 15*4882a593Smuzhiyun #define IR36021_MODE_MASK 0x20 16*4882a593Smuzhiyun #define IR36021_INTEL_MODE 0x00 17*4882a593Smuzhiyun #define IR36021_AMD_MODE 0x20 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* step the IR regulator in 5mV increments */ 20*4882a593Smuzhiyun #define IR_VDD_STEP_DOWN 5 21*4882a593Smuzhiyun #define IR_VDD_STEP_UP 5 22*4882a593Smuzhiyun int adjust_vdd(ulong vdd_override); 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #endif /* __VID_H_ */ 25