1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011 Freescale Semiconductor 3*4882a593Smuzhiyun * Author: Shengzhou Liu <Shengzhou.Liu@freescale.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file provides support for the QIXIS of some Freescale reference boards. 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __QIXIS_H_ 11*4882a593Smuzhiyun #define __QIXIS_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct qixis { 14*4882a593Smuzhiyun u8 id; /* ID value uniquely identifying each QDS board type */ 15*4882a593Smuzhiyun u8 arch; /* Board version information */ 16*4882a593Smuzhiyun u8 scver; /* QIXIS Version Register */ 17*4882a593Smuzhiyun u8 model; /* Information of software programming model version */ 18*4882a593Smuzhiyun u8 tagdata; 19*4882a593Smuzhiyun u8 ctl_sys; 20*4882a593Smuzhiyun u8 aux; /* Auxiliary Register,0x06 */ 21*4882a593Smuzhiyun u8 clk_spd; 22*4882a593Smuzhiyun u8 stat_dut; 23*4882a593Smuzhiyun u8 stat_sys; 24*4882a593Smuzhiyun u8 stat_alrm; 25*4882a593Smuzhiyun u8 present; 26*4882a593Smuzhiyun u8 present2; /* Presence Status Register 2,0x0c */ 27*4882a593Smuzhiyun u8 rcw_ctl; 28*4882a593Smuzhiyun u8 ctl_led; 29*4882a593Smuzhiyun u8 i2cblk; 30*4882a593Smuzhiyun u8 rcfg_ctl; /* Reconfig Control Register,0x10 */ 31*4882a593Smuzhiyun u8 rcfg_st; 32*4882a593Smuzhiyun u8 dcm_ad; 33*4882a593Smuzhiyun u8 dcm_da; 34*4882a593Smuzhiyun u8 dcmd; 35*4882a593Smuzhiyun u8 dmsg; 36*4882a593Smuzhiyun u8 gdc; 37*4882a593Smuzhiyun u8 gdd; /* DCM Debug Data Register,0x17 */ 38*4882a593Smuzhiyun u8 dmack; 39*4882a593Smuzhiyun u8 res1[6]; 40*4882a593Smuzhiyun u8 watch; /* Watchdog Register,0x1F */ 41*4882a593Smuzhiyun u8 pwr_ctl[2]; /* Power Control Register,0x20 */ 42*4882a593Smuzhiyun u8 res2[2]; 43*4882a593Smuzhiyun u8 pwr_stat[4]; /* Power Status Register,0x24 */ 44*4882a593Smuzhiyun u8 res3[8]; 45*4882a593Smuzhiyun u8 clk_spd2[2]; /* SYSCLK clock Speed Register,0x30 */ 46*4882a593Smuzhiyun u8 res4[2]; 47*4882a593Smuzhiyun u8 sclk[3]; /* Clock Configuration Registers,0x34 */ 48*4882a593Smuzhiyun u8 res5; 49*4882a593Smuzhiyun u8 dclk[3]; 50*4882a593Smuzhiyun u8 res6; 51*4882a593Smuzhiyun u8 clk_dspd[3]; 52*4882a593Smuzhiyun u8 res7; 53*4882a593Smuzhiyun u8 rst_ctl; /* Reset Control Register,0x40 */ 54*4882a593Smuzhiyun u8 rst_stat; /* Reset Status Register */ 55*4882a593Smuzhiyun u8 rst_rsn; /* Reset Reason Register */ 56*4882a593Smuzhiyun u8 rst_frc[2]; /* Reset Force Registers,0x43 */ 57*4882a593Smuzhiyun u8 res8[11]; 58*4882a593Smuzhiyun u8 brdcfg[16]; /* Board Configuration Register,0x50 */ 59*4882a593Smuzhiyun u8 dutcfg[16]; 60*4882a593Smuzhiyun u8 rcw_ad[2]; /* RCW SRAM Address Registers,0x70 */ 61*4882a593Smuzhiyun u8 rcw_data; 62*4882a593Smuzhiyun u8 res9[5]; 63*4882a593Smuzhiyun u8 post_ctl; 64*4882a593Smuzhiyun u8 post_stat; 65*4882a593Smuzhiyun u8 post_dat[2]; 66*4882a593Smuzhiyun u8 pi_d[4]; 67*4882a593Smuzhiyun u8 gpio_io[4]; 68*4882a593Smuzhiyun u8 gpio_dir[4]; 69*4882a593Smuzhiyun u8 res10[20]; 70*4882a593Smuzhiyun u8 rjtag_ctl; 71*4882a593Smuzhiyun u8 rjtag_dat; 72*4882a593Smuzhiyun u8 res11[2]; 73*4882a593Smuzhiyun u8 trig_src[4]; 74*4882a593Smuzhiyun u8 trig_dst[4]; 75*4882a593Smuzhiyun u8 trig_stat; 76*4882a593Smuzhiyun u8 res12[3]; 77*4882a593Smuzhiyun u8 trig_ctr[4]; 78*4882a593Smuzhiyun u8 res13[16]; 79*4882a593Smuzhiyun u8 clk_freq[6]; /* Clock Measurement Registers */ 80*4882a593Smuzhiyun u8 res_c6[8]; 81*4882a593Smuzhiyun u8 clk_base[2]; /* Clock Frequency Base Reg */ 82*4882a593Smuzhiyun u8 res_d0[8]; 83*4882a593Smuzhiyun u8 cms[2]; /* Core Management Space Address Register, 0xD8 */ 84*4882a593Smuzhiyun u8 res_c0[6]; 85*4882a593Smuzhiyun u8 aux2[4]; /* Auxiliary Registers,0xE0 */ 86*4882a593Smuzhiyun u8 res14[10]; 87*4882a593Smuzhiyun u8 aux_ad; 88*4882a593Smuzhiyun u8 aux_da; 89*4882a593Smuzhiyun u8 res15[16]; 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun u8 qixis_read(unsigned int reg); 93*4882a593Smuzhiyun void qixis_write(unsigned int reg, u8 value); 94*4882a593Smuzhiyun u16 qixis_read_minor(void); 95*4882a593Smuzhiyun char *qixis_read_time(char *result); 96*4882a593Smuzhiyun char *qixis_read_tag(char *buf); 97*4882a593Smuzhiyun const char *byte_to_binary_mask(u8 val, u8 mask, char *buf); 98*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C_FPGA_ADDR 99*4882a593Smuzhiyun u8 qixis_read_i2c(unsigned int reg); 100*4882a593Smuzhiyun void qixis_write_i2c(unsigned int reg, u8 value); 101*4882a593Smuzhiyun #endif 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun #if defined(CONFIG_QIXIS_I2C_ACCESS) && defined(CONFIG_SYS_I2C_FPGA_ADDR) 104*4882a593Smuzhiyun #define QIXIS_READ(reg) qixis_read_i2c(offsetof(struct qixis, reg)) 105*4882a593Smuzhiyun #define QIXIS_WRITE(reg, value) \ 106*4882a593Smuzhiyun qixis_write_i2c(offsetof(struct qixis, reg), value) 107*4882a593Smuzhiyun #else 108*4882a593Smuzhiyun #define QIXIS_READ(reg) qixis_read(offsetof(struct qixis, reg)) 109*4882a593Smuzhiyun #define QIXIS_WRITE(reg, value) qixis_write(offsetof(struct qixis, reg), value) 110*4882a593Smuzhiyun #endif 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun #ifdef CONFIG_SYS_I2C_FPGA_ADDR 113*4882a593Smuzhiyun #define QIXIS_READ_I2C(reg) qixis_read_i2c(offsetof(struct qixis, reg)) 114*4882a593Smuzhiyun #define QIXIS_WRITE_I2C(reg, value) \ 115*4882a593Smuzhiyun qixis_write_i2c(offsetof(struct qixis, reg), value) 116*4882a593Smuzhiyun #endif 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun /* Use for SDHC adapter card type identification and operation */ 119*4882a593Smuzhiyun #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT 120*4882a593Smuzhiyun #define QIXIS_SDID_MASK 0x07 121*4882a593Smuzhiyun #define QIXIS_ESDHC_ADAPTER_TYPE_EMMC45 0x1 /* eMMC Card Rev4.5 */ 122*4882a593Smuzhiyun #define QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY 0x2 /* SD/MMC Legacy Card */ 123*4882a593Smuzhiyun #define QIXIS_ESDHC_ADAPTER_TYPE_EMMC44 0x3 /* eMMC Card Rev4.4 */ 124*4882a593Smuzhiyun #define QIXIS_ESDHC_ADAPTER_TYPE_RSV 0x4 /* Reserved */ 125*4882a593Smuzhiyun #define QIXIS_ESDHC_ADAPTER_TYPE_MMC 0x5 /* MMC Card */ 126*4882a593Smuzhiyun #define QIXIS_ESDHC_ADAPTER_TYPE_SD 0x6 /* SD Card Rev2.0 3.0 */ 127*4882a593Smuzhiyun #define QIXIS_ESDHC_NO_ADAPTER 0x7 /* No Card is Present*/ 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun #define QIXIS_SDCLKIN 0x08 130*4882a593Smuzhiyun #define QIXIS_SDCLKOUT 0x02 131*4882a593Smuzhiyun #define QIXIS_DAT5_6_7 0X02 132*4882a593Smuzhiyun #define QIXIS_DAT4 0X01 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define QIXIS_EVDD_BY_SDHC_VS 0x0c 135*4882a593Smuzhiyun #endif 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #endif 138