1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <errno.h>
9*4882a593Smuzhiyun #include <power/pmic.h>
10*4882a593Smuzhiyun #include <power/pfuze100_pmic.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #ifndef CONFIG_DM_PMIC_PFUZE100
pfuze_mode_init(struct pmic * p,u32 mode)13*4882a593Smuzhiyun int pfuze_mode_init(struct pmic *p, u32 mode)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun unsigned char offset, i, switch_num;
16*4882a593Smuzhiyun u32 id;
17*4882a593Smuzhiyun int ret;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun pmic_reg_read(p, PFUZE100_DEVICEID, &id);
20*4882a593Smuzhiyun id = id & 0xf;
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun if (id == 0) {
23*4882a593Smuzhiyun switch_num = 6;
24*4882a593Smuzhiyun offset = PFUZE100_SW1CMODE;
25*4882a593Smuzhiyun } else if (id == 1) {
26*4882a593Smuzhiyun switch_num = 4;
27*4882a593Smuzhiyun offset = PFUZE100_SW2MODE;
28*4882a593Smuzhiyun } else {
29*4882a593Smuzhiyun printf("Not supported, id=%d\n", id);
30*4882a593Smuzhiyun return -EINVAL;
31*4882a593Smuzhiyun }
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
34*4882a593Smuzhiyun if (ret < 0) {
35*4882a593Smuzhiyun printf("Set SW1AB mode error!\n");
36*4882a593Smuzhiyun return ret;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun for (i = 0; i < switch_num - 1; i++) {
40*4882a593Smuzhiyun ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
41*4882a593Smuzhiyun if (ret < 0) {
42*4882a593Smuzhiyun printf("Set switch 0x%x mode error!\n",
43*4882a593Smuzhiyun offset + i * SWITCH_SIZE);
44*4882a593Smuzhiyun return ret;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return ret;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
pfuze_common_init(unsigned char i2cbus)51*4882a593Smuzhiyun struct pmic *pfuze_common_init(unsigned char i2cbus)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct pmic *p;
54*4882a593Smuzhiyun int ret;
55*4882a593Smuzhiyun unsigned int reg;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun ret = power_pfuze100_init(i2cbus);
58*4882a593Smuzhiyun if (ret)
59*4882a593Smuzhiyun return NULL;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun p = pmic_get("PFUZE100");
62*4882a593Smuzhiyun ret = pmic_probe(p);
63*4882a593Smuzhiyun if (ret)
64*4882a593Smuzhiyun return NULL;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun pmic_reg_read(p, PFUZE100_DEVICEID, ®);
67*4882a593Smuzhiyun printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /* Set SW1AB stanby volage to 0.975V */
70*4882a593Smuzhiyun pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
71*4882a593Smuzhiyun reg &= ~SW1x_STBY_MASK;
72*4882a593Smuzhiyun reg |= SW1x_0_975V;
73*4882a593Smuzhiyun pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
76*4882a593Smuzhiyun pmic_reg_read(p, PFUZE100_SW1ABCONF, ®);
77*4882a593Smuzhiyun reg &= ~SW1xCONF_DVSSPEED_MASK;
78*4882a593Smuzhiyun reg |= SW1xCONF_DVSSPEED_4US;
79*4882a593Smuzhiyun pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun /* Set SW1C standby voltage to 0.975V */
82*4882a593Smuzhiyun pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
83*4882a593Smuzhiyun reg &= ~SW1x_STBY_MASK;
84*4882a593Smuzhiyun reg |= SW1x_0_975V;
85*4882a593Smuzhiyun pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
88*4882a593Smuzhiyun pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
89*4882a593Smuzhiyun reg &= ~SW1xCONF_DVSSPEED_MASK;
90*4882a593Smuzhiyun reg |= SW1xCONF_DVSSPEED_4US;
91*4882a593Smuzhiyun pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return p;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun #endif
96