1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2014 Freescale Semiconductor
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/io.h>
9*4882a593Smuzhiyun #include <fsl_csu.h>
10*4882a593Smuzhiyun #include <asm/arch/ns_access.h>
11*4882a593Smuzhiyun #include <asm/arch/fsl_serdes.h>
12*4882a593Smuzhiyun
set_devices_ns_access(unsigned long index,u16 val)13*4882a593Smuzhiyun void set_devices_ns_access(unsigned long index, u16 val)
14*4882a593Smuzhiyun {
15*4882a593Smuzhiyun u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
16*4882a593Smuzhiyun u32 *reg;
17*4882a593Smuzhiyun uint32_t tmp;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun reg = base + index / 2;
20*4882a593Smuzhiyun tmp = in_be32(reg);
21*4882a593Smuzhiyun if (index % 2 == 0) {
22*4882a593Smuzhiyun tmp &= 0x0000ffff;
23*4882a593Smuzhiyun tmp |= val << 16;
24*4882a593Smuzhiyun } else {
25*4882a593Smuzhiyun tmp &= 0xffff0000;
26*4882a593Smuzhiyun tmp |= val;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun out_be32(reg, tmp);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
enable_devices_ns_access(struct csu_ns_dev * ns_dev,uint32_t num)32*4882a593Smuzhiyun static void enable_devices_ns_access(struct csu_ns_dev *ns_dev, uint32_t num)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun int i;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun for (i = 0; i < num; i++)
37*4882a593Smuzhiyun set_devices_ns_access(ns_dev[i].ind, ns_dev[i].val);
38*4882a593Smuzhiyun }
39*4882a593Smuzhiyun
enable_layerscape_ns_access(void)40*4882a593Smuzhiyun void enable_layerscape_ns_access(void)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun #ifdef CONFIG_ARM64
43*4882a593Smuzhiyun if (current_el() == 3)
44*4882a593Smuzhiyun #endif
45*4882a593Smuzhiyun enable_devices_ns_access(ns_dev, ARRAY_SIZE(ns_dev));
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
set_pcie_ns_access(int pcie,u16 val)48*4882a593Smuzhiyun void set_pcie_ns_access(int pcie, u16 val)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun switch (pcie) {
51*4882a593Smuzhiyun #ifdef CONFIG_PCIE1
52*4882a593Smuzhiyun case PCIE1:
53*4882a593Smuzhiyun set_devices_ns_access(CSU_CSLX_PCIE1, val);
54*4882a593Smuzhiyun set_devices_ns_access(CSU_CSLX_PCIE1_IO, val);
55*4882a593Smuzhiyun return;
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun #ifdef CONFIG_PCIE2
58*4882a593Smuzhiyun case PCIE2:
59*4882a593Smuzhiyun set_devices_ns_access(CSU_CSLX_PCIE2, val);
60*4882a593Smuzhiyun set_devices_ns_access(CSU_CSLX_PCIE2_IO, val);
61*4882a593Smuzhiyun return;
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun #ifdef CONFIG_PCIE3
64*4882a593Smuzhiyun case PCIE3:
65*4882a593Smuzhiyun set_devices_ns_access(CSU_CSLX_PCIE3, val);
66*4882a593Smuzhiyun set_devices_ns_access(CSU_CSLX_PCIE3_IO, val);
67*4882a593Smuzhiyun return;
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun default:
70*4882a593Smuzhiyun debug("The PCIE%d doesn't exist!\n", pcie);
71*4882a593Smuzhiyun return;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun }
74