1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * Copyright 2010-2011 Freescale Semiconductor 3*4882a593Smuzhiyun * Author: Timur Tabi <timur@freescale.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * This file provides support for the ngPIXIS, a board-specific FPGA used on 8*4882a593Smuzhiyun * some Freescale reference boards. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* ngPIXIS register set. Hopefully, this won't change too much over time. 12*4882a593Smuzhiyun * Feel free to add board-specific #ifdefs where necessary. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun typedef struct ngpixis { 15*4882a593Smuzhiyun u8 id; 16*4882a593Smuzhiyun u8 arch; 17*4882a593Smuzhiyun u8 scver; 18*4882a593Smuzhiyun u8 csr; 19*4882a593Smuzhiyun u8 rst; 20*4882a593Smuzhiyun u8 serclk; 21*4882a593Smuzhiyun u8 aux; 22*4882a593Smuzhiyun u8 spd; 23*4882a593Smuzhiyun u8 brdcfg0; 24*4882a593Smuzhiyun u8 brdcfg1; /* On some boards, this register is called 'dma' */ 25*4882a593Smuzhiyun u8 addr; 26*4882a593Smuzhiyun u8 brdcfg2; 27*4882a593Smuzhiyun u8 gpiodir; 28*4882a593Smuzhiyun u8 data; 29*4882a593Smuzhiyun u8 led; 30*4882a593Smuzhiyun u8 tag; 31*4882a593Smuzhiyun u8 vctl; 32*4882a593Smuzhiyun u8 vstat; 33*4882a593Smuzhiyun u8 vcfgen0; 34*4882a593Smuzhiyun u8 res4; 35*4882a593Smuzhiyun u8 ocmcsr; 36*4882a593Smuzhiyun u8 ocmmsg; 37*4882a593Smuzhiyun u8 gmdbg; 38*4882a593Smuzhiyun u8 res5[2]; 39*4882a593Smuzhiyun u8 sclk[3]; 40*4882a593Smuzhiyun u8 dclk[3]; 41*4882a593Smuzhiyun u8 watch; 42*4882a593Smuzhiyun struct { 43*4882a593Smuzhiyun u8 sw; 44*4882a593Smuzhiyun u8 en; 45*4882a593Smuzhiyun } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */ 46*4882a593Smuzhiyun } __attribute__ ((packed)) ngpixis_t; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /* Pointer to the PIXIS register set */ 49*4882a593Smuzhiyun #define pixis ((ngpixis_t *)PIXIS_BASE) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* The PIXIS SW register that corresponds to board switch X, where x >= 1 */ 52*4882a593Smuzhiyun #define PIXIS_SW(x) (pixis->s[(x) - 1].sw) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* The PIXIS EN register that corresponds to board switch X, where x >= 1 */ 55*4882a593Smuzhiyun #define PIXIS_EN(x) (pixis->s[(x) - 1].en) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun u8 pixis_read(unsigned int reg); 58*4882a593Smuzhiyun void pixis_write(unsigned int reg, u8 value); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #define PIXIS_READ(reg) pixis_read(offsetof(ngpixis_t, reg)) 61*4882a593Smuzhiyun #define PIXIS_WRITE(reg, value) pixis_write(offsetof(ngpixis_t, reg), value) 62