1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2004, 2011 Freescale Semiconductor. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * CADMUS Board System Registers 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifndef CONFIG_SYS_CADMUS_BASE_REG 15*4882a593Smuzhiyun #define CONFIG_SYS_CADMUS_BASE_REG (CADMUS_BASE_ADDR + 0x4000) 16*4882a593Smuzhiyun #endif 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun typedef struct cadmus_reg { 19*4882a593Smuzhiyun u_char cm_ver; /* Board version */ 20*4882a593Smuzhiyun u_char cm_csr; /* General control/status */ 21*4882a593Smuzhiyun u_char cm_rst; /* Reset control */ 22*4882a593Smuzhiyun u_char cm_hsclk; /* High speed clock */ 23*4882a593Smuzhiyun u_char cm_hsxclk; /* High speed clock extended */ 24*4882a593Smuzhiyun u_char cm_led; /* LED data */ 25*4882a593Smuzhiyun u_char cm_pci; /* PCI control/status */ 26*4882a593Smuzhiyun u_char cm_dma; /* DMA control */ 27*4882a593Smuzhiyun u_char cm_reserved[248]; /* Total 256 bytes */ 28*4882a593Smuzhiyun } cadmus_reg_t; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun unsigned int get_board_version(void)32*4882a593Smuzhiyunget_board_version(void) 33*4882a593Smuzhiyun { 34*4882a593Smuzhiyun volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun return cadmus->cm_ver; 37*4882a593Smuzhiyun } 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun unsigned long get_clock_freq(void)41*4882a593Smuzhiyunget_clock_freq(void) 42*4882a593Smuzhiyun { 43*4882a593Smuzhiyun volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun if (pci1_speed == 0) { 48*4882a593Smuzhiyun return 33333333; 49*4882a593Smuzhiyun } else if (pci1_speed == 1) { 50*4882a593Smuzhiyun return 66666666; 51*4882a593Smuzhiyun } else { 52*4882a593Smuzhiyun /* Really, unknown. Be safe? */ 53*4882a593Smuzhiyun return 33333333; 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun } 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun unsigned int get_pci_slot(void)59*4882a593Smuzhiyunget_pci_slot(void) 60*4882a593Smuzhiyun { 61*4882a593Smuzhiyun volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * PCI slot in USER bits CSR[6:7] by convention. 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun return ((cadmus->cm_csr >> 6) & 0x3) + 1; 67*4882a593Smuzhiyun } 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun unsigned int get_pci_dual(void)71*4882a593Smuzhiyunget_pci_dual(void) 72*4882a593Smuzhiyun { 73*4882a593Smuzhiyun volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * PCI DUAL in CM_PCI[3] 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun return cadmus->cm_pci & 0x10; 79*4882a593Smuzhiyun } 80