1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/mmu.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 11*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 12*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 13*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 14*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 18*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 19*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 22*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 23*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* TLB 1 */ 29*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 30*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 31*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_1M, 1), 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #ifndef CONFIG_SPL_BUILD 34*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, 35*4882a593Smuzhiyun MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 36*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_64M, 1), 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #ifdef CONFIG_PCI 39*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, 40*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 41*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_256M, 1), 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, 44*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 45*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_256K, 1), 46*4882a593Smuzhiyun #endif 47*4882a593Smuzhiyun #endif 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, 50*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 51*4882a593Smuzhiyun 0, 4, BOOKE_PAGESZ_64K, 1), 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 54*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 55*4882a593Smuzhiyun 0, 5, BOOKE_PAGESZ_64K, 1), 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, 58*4882a593Smuzhiyun CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, 59*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 60*4882a593Smuzhiyun 0, 6, BOOKE_PAGESZ_256K, 1), 61*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000, 62*4882a593Smuzhiyun CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000, 63*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 64*4882a593Smuzhiyun 0, 7, BOOKE_PAGESZ_256K, 1), 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #if defined(CONFIG_SYS_RAMBOOT) || \ 67*4882a593Smuzhiyun (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)) 68*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, 69*4882a593Smuzhiyun CONFIG_SYS_DDR_SDRAM_BASE, 70*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 71*4882a593Smuzhiyun 0, 8, BOOKE_PAGESZ_256M, 1), 72*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 73*4882a593Smuzhiyun CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, 74*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 75*4882a593Smuzhiyun 0, 9, BOOKE_PAGESZ_256M, 1), 76*4882a593Smuzhiyun #endif 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #ifdef CONFIG_SYS_INIT_L2_ADDR 79*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, 80*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, 81*4882a593Smuzhiyun 0, 12, BOOKE_PAGESZ_256K, 1) 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 86