1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <i2c.h>
9*4882a593Smuzhiyun #include <asm/fsl_law.h>
10*4882a593Smuzhiyun #include <fsl_ddr_sdram.h>
11*4882a593Smuzhiyun #include <fsl_ddr_dimm_params.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "cpld.h"
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #define C29XPCIE_HARDWARE_REVA 0x40
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * Micron MT41J128M16HA-15E
18*4882a593Smuzhiyun * */
19*4882a593Smuzhiyun dimm_params_t ddr_raw_timing = {
20*4882a593Smuzhiyun .n_ranks = 1,
21*4882a593Smuzhiyun .rank_density = 536870912u,
22*4882a593Smuzhiyun .capacity = 536870912u,
23*4882a593Smuzhiyun .primary_sdram_width = 32,
24*4882a593Smuzhiyun .ec_sdram_width = 8,
25*4882a593Smuzhiyun .registered_dimm = 0,
26*4882a593Smuzhiyun .mirrored_dimm = 0,
27*4882a593Smuzhiyun .n_row_addr = 14,
28*4882a593Smuzhiyun .n_col_addr = 10,
29*4882a593Smuzhiyun .n_banks_per_sdram_device = 8,
30*4882a593Smuzhiyun .edc_config = 2,
31*4882a593Smuzhiyun .burst_lengths_bitmask = 0x0c,
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun .tckmin_x_ps = 1650,
34*4882a593Smuzhiyun .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
35*4882a593Smuzhiyun .taa_ps = 14050,
36*4882a593Smuzhiyun .twr_ps = 15000,
37*4882a593Smuzhiyun .trcd_ps = 13500,
38*4882a593Smuzhiyun .trrd_ps = 75000,
39*4882a593Smuzhiyun .trp_ps = 13500,
40*4882a593Smuzhiyun .tras_ps = 40000,
41*4882a593Smuzhiyun .trc_ps = 49500,
42*4882a593Smuzhiyun .trfc_ps = 160000,
43*4882a593Smuzhiyun .twtr_ps = 75000,
44*4882a593Smuzhiyun .trtp_ps = 75000,
45*4882a593Smuzhiyun .refresh_rate_ps = 7800000,
46*4882a593Smuzhiyun .tfaw_ps = 30000,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
fsl_ddr_get_dimm_params(dimm_params_t * pdimm,unsigned int controller_number,unsigned int dimm_number)49*4882a593Smuzhiyun int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
50*4882a593Smuzhiyun unsigned int controller_number,
51*4882a593Smuzhiyun unsigned int dimm_number)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun const char dimm_model[] = "Fixed DDR on board";
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun if ((controller_number == 0) && (dimm_number == 0)) {
56*4882a593Smuzhiyun memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
57*4882a593Smuzhiyun memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
58*4882a593Smuzhiyun memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
59*4882a593Smuzhiyun }
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
fsl_ddr_board_options(memctl_options_t * popts,dimm_params_t * pdimm,unsigned int ctrl_num)64*4882a593Smuzhiyun void fsl_ddr_board_options(memctl_options_t *popts,
65*4882a593Smuzhiyun dimm_params_t *pdimm,
66*4882a593Smuzhiyun unsigned int ctrl_num)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
69*4882a593Smuzhiyun int i;
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun popts->clk_adjust = 4;
72*4882a593Smuzhiyun popts->cpo_override = 0x1f;
73*4882a593Smuzhiyun popts->write_data_delay = 4;
74*4882a593Smuzhiyun popts->half_strength_driver_enable = 1;
75*4882a593Smuzhiyun popts->bstopre = 0x3cf;
76*4882a593Smuzhiyun popts->quad_rank_present = 1;
77*4882a593Smuzhiyun popts->rtt_override = 1;
78*4882a593Smuzhiyun popts->rtt_override_value = 1;
79*4882a593Smuzhiyun popts->dynamic_power = 1;
80*4882a593Smuzhiyun /* Write leveling override */
81*4882a593Smuzhiyun popts->wrlvl_en = 1;
82*4882a593Smuzhiyun popts->wrlvl_override = 1;
83*4882a593Smuzhiyun popts->wrlvl_sample = 0xf;
84*4882a593Smuzhiyun popts->wrlvl_start = 0x4;
85*4882a593Smuzhiyun popts->trwt_override = 1;
86*4882a593Smuzhiyun popts->trwt = 0;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (in_8(&cpld_data->hwver) == C29XPCIE_HARDWARE_REVA)
89*4882a593Smuzhiyun popts->ecc_mode = 0;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
92*4882a593Smuzhiyun popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
93*4882a593Smuzhiyun popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
get_spd(generic_spd_eeprom_t * spd,u8 i2c_address)97*4882a593Smuzhiyun void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun int ret = i2c_read(i2c_address, 0, 2, (uint8_t *)spd,
100*4882a593Smuzhiyun sizeof(generic_spd_eeprom_t));
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun if (ret) {
103*4882a593Smuzhiyun printf("DDR: failed to read SPD from address %u\n",
104*4882a593Smuzhiyun i2c_address);
105*4882a593Smuzhiyun memset(spd, 0, sizeof(generic_spd_eeprom_t));
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun }
108