1*4882a593Smuzhiyun /** 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor 3*4882a593Smuzhiyun * Author: Mingkai Hu <Mingkai.Hu@freescale.com> 4*4882a593Smuzhiyun * Po Liu <Po.Liu@freescale.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * This file provides support for the ngPIXIS, a board-specific FPGA used on 9*4882a593Smuzhiyun * some Freescale reference boards. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * CPLD register set. Feel free to add board-specific #ifdefs where necessary. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct cpld_data { 16*4882a593Smuzhiyun u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */ 17*4882a593Smuzhiyun u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */ 18*4882a593Smuzhiyun u8 hwver; /* 0x2 - Hardware Version Register */ 19*4882a593Smuzhiyun u8 cpldver; /* 0x3 - Software Version Register */ 20*4882a593Smuzhiyun u8 res[12]; 21*4882a593Smuzhiyun u8 rstcon; /* 0x10 - Reset control register */ 22*4882a593Smuzhiyun u8 flhcsr; /* 0x11 - Flash control and status Register */ 23*4882a593Smuzhiyun u8 wdcsr; /* 0x12 - Watchdog control and status Register */ 24*4882a593Smuzhiyun u8 wdkick; /* 0x13 - Watchdog kick Register */ 25*4882a593Smuzhiyun u8 fancsr; /* 0x14 - Fan control and status Register */ 26*4882a593Smuzhiyun u8 ledcsr; /* 0x15 - LED control and status Register */ 27*4882a593Smuzhiyun u8 misccsr; /* 0x16 - Misc control and status Register */ 28*4882a593Smuzhiyun u8 bootor; /* 0x17 - Boot configure override Register */ 29*4882a593Smuzhiyun u8 bootcfg1; /* 0x18 - Boot configure 1 Register */ 30*4882a593Smuzhiyun u8 bootcfg2; /* 0x19 - Boot configure 2 Register */ 31*4882a593Smuzhiyun u8 bootcfg3; /* 0x1a - Boot configure 3 Register */ 32*4882a593Smuzhiyun u8 bootcfg4; /* 0x1b - Boot configure 4 Register */ 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define CPLD_BANKSEL_EN 0x02 36*4882a593Smuzhiyun #define CPLD_BANKSEL_MASK 0x3f 37*4882a593Smuzhiyun #define CPLD_SELECT_BANK1 0xc0 38*4882a593Smuzhiyun #define CPLD_SELECT_BANK2 0x80 39*4882a593Smuzhiyun #define CPLD_SELECT_BANK3 0x40 40*4882a593Smuzhiyun #define CPLD_SELECT_BANK4 0x00 41