1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <asm/processor.h>
9*4882a593Smuzhiyun #include <asm/mmu.h>
10*4882a593Smuzhiyun #include <asm/cache.h>
11*4882a593Smuzhiyun #include <asm/immap_85xx.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun #include <miiphy.h>
14*4882a593Smuzhiyun #include <linux/libfdt.h>
15*4882a593Smuzhiyun #include <fdt_support.h>
16*4882a593Smuzhiyun #include <fsl_mdio.h>
17*4882a593Smuzhiyun #include <tsec.h>
18*4882a593Smuzhiyun #include <mmc.h>
19*4882a593Smuzhiyun #include <netdev.h>
20*4882a593Smuzhiyun #include <pci.h>
21*4882a593Smuzhiyun #include <fsl_ifc.h>
22*4882a593Smuzhiyun #include <asm/fsl_pci.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include "cpld.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
27*4882a593Smuzhiyun
checkboard(void)28*4882a593Smuzhiyun int checkboard(void)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct cpu_type *cpu = gd->arch.cpu;
31*4882a593Smuzhiyun struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun printf("Board: %sPCIe, ", cpu->name);
34*4882a593Smuzhiyun printf("CPLD Ver: 0x%02x\n", in_8(&cpld_data->cpldver));
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun return 0;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
board_early_init_f(void)39*4882a593Smuzhiyun int board_early_init_f(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Clock configuration to access CPLD using IFC(GPCM) */
44*4882a593Smuzhiyun setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun return 0;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
board_early_init_r(void)49*4882a593Smuzhiyun int board_early_init_r(void)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
52*4882a593Smuzhiyun int flash_esel = find_tlb_idx((void *)flashbase, 1);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * Remap Boot flash region to caching-inhibited
56*4882a593Smuzhiyun * so that flash can be erased properly.
57*4882a593Smuzhiyun */
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Flush d-cache and invalidate i-cache of any FLASH data */
60*4882a593Smuzhiyun flush_dcache();
61*4882a593Smuzhiyun invalidate_icache();
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun if (flash_esel == -1) {
64*4882a593Smuzhiyun /* very unlikely unless something is messed up */
65*4882a593Smuzhiyun puts("Error: Could not find TLB for FLASH BASE\n");
66*4882a593Smuzhiyun flash_esel = 1; /* give our best effort to continue */
67*4882a593Smuzhiyun } else {
68*4882a593Smuzhiyun /* invalidate existing TLB entry for flash */
69*4882a593Smuzhiyun disable_tlb(flash_esel);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
73*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
74*4882a593Smuzhiyun 0, flash_esel, BOOKE_PAGESZ_64M, 1);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun #ifdef CONFIG_PCI
pci_init_board(void)80*4882a593Smuzhiyun void pci_init_board(void)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun fsl_pcie_init_board(0);
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun #endif /* ifdef CONFIG_PCI */
85*4882a593Smuzhiyun
board_eth_init(bd_t * bis)86*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
87*4882a593Smuzhiyun {
88*4882a593Smuzhiyun #ifdef CONFIG_TSEC_ENET
89*4882a593Smuzhiyun struct fsl_pq_mdio_info mdio_info;
90*4882a593Smuzhiyun struct tsec_info_struct tsec_info[2];
91*4882a593Smuzhiyun int num = 0;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #ifdef CONFIG_TSEC1
94*4882a593Smuzhiyun SET_STD_TSEC_INFO(tsec_info[num], 1);
95*4882a593Smuzhiyun num++;
96*4882a593Smuzhiyun #endif
97*4882a593Smuzhiyun #ifdef CONFIG_TSEC2
98*4882a593Smuzhiyun SET_STD_TSEC_INFO(tsec_info[num], 2);
99*4882a593Smuzhiyun num++;
100*4882a593Smuzhiyun #endif
101*4882a593Smuzhiyun if (!num) {
102*4882a593Smuzhiyun printf("No TSECs initialized\n");
103*4882a593Smuzhiyun return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /* Register 1G MDIO bus */
107*4882a593Smuzhiyun mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
108*4882a593Smuzhiyun mdio_info.name = DEFAULT_MII_NAME;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun fsl_pq_mdio_init(bis, &mdio_info);
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun tsec_eth_init(bis, tsec_info, num);
113*4882a593Smuzhiyun #endif
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun return pci_eth_init(bis);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun #if defined(CONFIG_OF_BOARD_SETUP)
fdt_del_sec(void * blob,int offset)119*4882a593Smuzhiyun void fdt_del_sec(void *blob, int offset)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun int nodeoff = 0;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0",
124*4882a593Smuzhiyun CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET
125*4882a593Smuzhiyun + offset * CONFIG_SYS_FSL_SEC_IDX_OFFSET)) >= 0) {
126*4882a593Smuzhiyun fdt_del_node(blob, nodeoff);
127*4882a593Smuzhiyun offset++;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
ft_board_setup(void * blob,bd_t * bd)131*4882a593Smuzhiyun int ft_board_setup(void *blob, bd_t *bd)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun phys_addr_t base;
134*4882a593Smuzhiyun phys_size_t size;
135*4882a593Smuzhiyun struct cpu_type *cpu;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun cpu = gd->arch.cpu;
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun ft_cpu_setup(blob, bd);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun base = env_get_bootm_low();
142*4882a593Smuzhiyun size = env_get_bootm_size();
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun #if defined(CONFIG_PCI)
145*4882a593Smuzhiyun FT_FSL_PCI_SETUP;
146*4882a593Smuzhiyun #endif
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun fdt_fixup_memory(blob, (u64)base, (u64)size);
149*4882a593Smuzhiyun if (cpu->soc_ver == SVR_C291)
150*4882a593Smuzhiyun fdt_del_sec(blob, 1);
151*4882a593Smuzhiyun else if (cpu->soc_ver == SVR_C292)
152*4882a593Smuzhiyun fdt_del_sec(blob, 2);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return 0;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun #endif
157