1*4882a593SmuzhiyunOverview 2*4882a593Smuzhiyun========= 3*4882a593SmuzhiyunC29XPCIE board is a series of Freescale PCIe add-in cards to perform 4*4882a593Smuzhiyunas public key crypto accelerator or secure key management module. 5*4882a593SmuzhiyunIt includes C293PCIE board, C293PCIE board and C291PCIE board. 6*4882a593SmuzhiyunThe Freescale C29x family is a high performance crypto co-processor. 7*4882a593SmuzhiyunIt combines a single e500v2 core with necessary SEC engines. 8*4882a593Smuzhiyun(maximum core frequency 1000/1200 MHz). 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThe C29xPCIE board features are as follows: 11*4882a593SmuzhiyunMemory subsystem: 12*4882a593Smuzhiyun - 512Mbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus) 13*4882a593Smuzhiyun - 64 Mbyte NOR flash single-chip memory 14*4882a593Smuzhiyun - 4 Gbyte NAND flash memory 15*4882a593Smuzhiyun - 1 Mbit AT24C1024 I2C EEPROM 16*4882a593Smuzhiyun - 16 Mbyte SPI memory 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunInterfaces: 19*4882a593Smuzhiyun - 10/100/1000 BaseT Ethernet ports: 20*4882a593Smuzhiyun - eTSEC1, RGMII: one 10/100/1000 port 21*4882a593Smuzhiyun - eTSEC2, RGMII: one 10/100/1000 port 22*4882a593Smuzhiyun - DUART interface: 23*4882a593Smuzhiyun - DUART interface: supports two UARTs up to 115200 bps for 24*4882a593Smuzhiyun console display 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunBoard connectors: 27*4882a593Smuzhiyun - Mini-ITX power supply connector 28*4882a593Smuzhiyun - JTAG/COP for debugging 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunPhysical Memory Map on C29xPCIE 31*4882a593Smuzhiyun=============================== 32*4882a593SmuzhiyunAddress Start Address End Memory type 33*4882a593Smuzhiyun0x0_0000_0000 - 0x0_1fff_ffff 512MB DDR 34*4882a593Smuzhiyun0xc_0000_0000 - 0xc_8fff_ffff 256MB PCIE memory 35*4882a593Smuzhiyun0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash 36*4882a593Smuzhiyun0xf_ffb0_0000 - 0xf_ffb7_ffff 512KB SRAM 37*4882a593Smuzhiyun0xf_ffc0_0000 - 0xf_ffc0_ffff 64KB PCIE IO 38*4882a593Smuzhiyun0xf_ffdf_0000 - 0xf_ffdf_0fff 4KB CPLD 39*4882a593Smuzhiyun0xf_ffe0_0000 - 0xf_ffef_ffff 1MB CCSR 40*4882a593Smuzhiyun 41*4882a593SmuzhiyunSerial Port Configuration on C29xPCIE 42*4882a593Smuzhiyun===================================== 43*4882a593SmuzhiyunConfigure the serial port of the attached computer with the following values: 44*4882a593Smuzhiyun -Data rate: 115200 bps 45*4882a593Smuzhiyun -Number of data bits: 8 46*4882a593Smuzhiyun -Parity: None 47*4882a593Smuzhiyun -Number of Stop bits: 1 48*4882a593Smuzhiyun -Flow Control: Hardware/None 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunSettings of DIP-switch 51*4882a593Smuzhiyun====================== 52*4882a593Smuzhiyun SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash 53*4882a593Smuzhiyun SW5[1:4]= 0110 and SW5[6]=0 for boot from SPI flash 54*4882a593SmuzhiyunNote: 1 stands for 'off', 0 stands for 'on' 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunBuild and program U-Boot to NOR flash 57*4882a593Smuzhiyun================================== 58*4882a593Smuzhiyun1. Build u-boot.bin image example: 59*4882a593Smuzhiyun export ARCH=powerpc 60*4882a593Smuzhiyun export CROSS_COMPILE=/your_path/powerpc-linux-gnu- 61*4882a593Smuzhiyun make C293PCIE 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun2. Program u-boot.bin into NOR flash 64*4882a593Smuzhiyun => tftp $loadaddr $uboot 65*4882a593Smuzhiyun => protect off eff40000 +$filesize 66*4882a593Smuzhiyun => erase eff40000 +$filesize 67*4882a593Smuzhiyun => cp.b $loadaddr eff40000 $filesize 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun3. Check SW5[1:4]= 1111 and SW5[6]=0, then power on. 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunAlternate NOR bank 72*4882a593Smuzhiyun================== 73*4882a593SmuzhiyunThere are four banks in C29XPCIE board, example to change bank booting: 74*4882a593Smuzhiyun1. Program u-boot.bin into alternate NOR bank 75*4882a593Smuzhiyun => tftp $loadaddr $uboot 76*4882a593Smuzhiyun => protect off e9f40000 +$filesize 77*4882a593Smuzhiyun => erase e9f40000 +$filesize 78*4882a593Smuzhiyun => cp.b $loadaddr e9f40000 $filesize 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun2. Switch to alternate NOR bank 81*4882a593Smuzhiyun => cpld_cmd reset altbank [bank] 82*4882a593Smuzhiyun - [bank] bank value select 1-4 83*4882a593Smuzhiyun - bank 1 on the flash 0x0000000~0x0ffffff 84*4882a593Smuzhiyun - bank 2 on the flash 0x1000000~0x1ffffff 85*4882a593Smuzhiyun - bank 3 on the flash 0x2000000~0x2ffffff 86*4882a593Smuzhiyun - bank 4 on the flash 0x3000000~0x3ffffff 87*4882a593Smuzhiyun or set SW5[7]= ON/OFF and SW5[7]= ON/OFF, then power on again. 88*4882a593Smuzhiyun 89*4882a593SmuzhiyunBuild and program U-Boot to SPI flash 90*4882a593Smuzhiyun================================== 91*4882a593Smuzhiyun1. Build u-boot-spi.bin image 92*4882a593Smuzhiyun make C29xPCIE_SPIFLASH_config; make 93*4882a593Smuzhiyun Need the boot_format tool to generate u-boot-spi.bin from the u-boot.bin. 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun2. Program u-boot-spi.bin into SPI flash 96*4882a593Smuzhiyun => tftp $loadaddr $uboot-spi 97*4882a593Smuzhiyun => sf erase 0 100000 98*4882a593Smuzhiyun => sf write $loadaddr 0 $filesize 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun3. Check SW5[1:4]= 0110 and SW5[6]=0, then power on. 101