1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2013 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/fsl_law.h> 9*4882a593Smuzhiyun #include <asm/mmu.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct law_entry law_table[] = { 12*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_IFC), 13*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_BASE_PHYS 14*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), 15*4882a593Smuzhiyun #endif 16*4882a593Smuzhiyun #ifdef CONFIG_SYS_FPGA_BASE_PHYS 17*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FPGA_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_IFC), 18*4882a593Smuzhiyun #endif 19*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M, 20*4882a593Smuzhiyun LAW_TRGT_IF_DSP_CCSR), 21*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_32M, 22*4882a593Smuzhiyun LAW_TRGT_IF_OCN_DSP), 23*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FSL_DSP_M3_RAM_ADDR, LAW_SIZE_32K, 24*4882a593Smuzhiyun LAW_TRGT_IF_CLASS_DSP), 25*4882a593Smuzhiyun SET_LAW(CONFIG_SYS_FSL_DSP_DDR_ADDR, LAW_SIZE_1G, 26*4882a593Smuzhiyun LAW_TRGT_IF_CLASS_DSP) 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun int num_law_entries = ARRAY_SIZE(law_table); 30