1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2011-2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #include <common.h> 8*4882a593Smuzhiyun #include <asm/mmu.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct fsl_e_tlb_entry tlb_table[] = { 11*4882a593Smuzhiyun /* TLB 0 - for temp stack in cache */ 12*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, 13*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 14*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 15*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , 16*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, 17*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 18*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 19*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , 20*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, 21*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 22*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 23*4882a593Smuzhiyun SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , 24*4882a593Smuzhiyun CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, 25*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 26*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 0), 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /* TLB 1 */ 29*4882a593Smuzhiyun /* *I*** - Covers boot page */ 30*4882a593Smuzhiyun SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, 31*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 32*4882a593Smuzhiyun 0, 0, BOOKE_PAGESZ_4K, 1), 33*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT 34*4882a593Smuzhiyun SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, 35*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 36*4882a593Smuzhiyun 0, 10, BOOKE_PAGESZ_4K, 1), 37*4882a593Smuzhiyun #endif 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* *I*G* - CCSRBAR (PA) */ 40*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, 41*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 42*4882a593Smuzhiyun 0, 1, BOOKE_PAGESZ_1M, 1), 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* CCSRBAR (DSP) */ 45*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR, 46*4882a593Smuzhiyun CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, 47*4882a593Smuzhiyun MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 48*4882a593Smuzhiyun 0, 2, BOOKE_PAGESZ_1M, 1), 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) 51*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, 52*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, 0, 53*4882a593Smuzhiyun 0, 8, BOOKE_PAGESZ_1G, 1), 54*4882a593Smuzhiyun #endif 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, 57*4882a593Smuzhiyun MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 58*4882a593Smuzhiyun 0, 3, BOOKE_PAGESZ_1M, 1) 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun int num_tlb_entries = ARRAY_SIZE(tlb_table); 63