1*4882a593Smuzhiyun /* Copyright 2013 Freescale Semiconductor, Inc.
2*4882a593Smuzhiyun *
3*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <console.h>
8*4882a593Smuzhiyun #include <environment.h>
9*4882a593Smuzhiyun #include <asm/spl.h>
10*4882a593Smuzhiyun #include <malloc.h>
11*4882a593Smuzhiyun #include <ns16550.h>
12*4882a593Smuzhiyun #include <nand.h>
13*4882a593Smuzhiyun #include <i2c.h>
14*4882a593Smuzhiyun #include "../common/qixis.h"
15*4882a593Smuzhiyun #include "b4860qds_qixis.h"
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
get_effective_memsize(void)19*4882a593Smuzhiyun phys_size_t get_effective_memsize(void)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun return CONFIG_SYS_L3_SIZE;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
get_board_sys_clk(void)24*4882a593Smuzhiyun unsigned long get_board_sys_clk(void)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun switch ((sysclk_conf & 0x0C) >> 2) {
29*4882a593Smuzhiyun case QIXIS_CLK_100:
30*4882a593Smuzhiyun return 100000000;
31*4882a593Smuzhiyun case QIXIS_CLK_125:
32*4882a593Smuzhiyun return 125000000;
33*4882a593Smuzhiyun case QIXIS_CLK_133:
34*4882a593Smuzhiyun return 133333333;
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun return 66666666;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
get_board_ddr_clk(void)39*4882a593Smuzhiyun unsigned long get_board_ddr_clk(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun switch (ddrclk_conf & 0x03) {
44*4882a593Smuzhiyun case QIXIS_CLK_100:
45*4882a593Smuzhiyun return 100000000;
46*4882a593Smuzhiyun case QIXIS_CLK_125:
47*4882a593Smuzhiyun return 125000000;
48*4882a593Smuzhiyun case QIXIS_CLK_133:
49*4882a593Smuzhiyun return 133333333;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun return 66666666;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
board_init_f(ulong bootflag)54*4882a593Smuzhiyun void board_init_f(ulong bootflag)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun u32 plat_ratio, sys_clk, uart_clk;
57*4882a593Smuzhiyun ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
60*4882a593Smuzhiyun memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun /* Update GD pointer */
63*4882a593Smuzhiyun gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* compiler optimization barrier needed for GCC >= 3.4 */
66*4882a593Smuzhiyun __asm__ __volatile__("" : : : "memory");
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun console_init_f();
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* initialize selected port with appropriate baud rate */
71*4882a593Smuzhiyun sys_clk = get_board_sys_clk();
72*4882a593Smuzhiyun plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
73*4882a593Smuzhiyun uart_clk = sys_clk * plat_ratio / 2;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
76*4882a593Smuzhiyun uart_clk / 16 / CONFIG_BAUDRATE);
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
board_init_r(gd_t * gd,ulong dest_addr)81*4882a593Smuzhiyun void board_init_r(gd_t *gd, ulong dest_addr)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun bd_t *bd;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun bd = (bd_t *)(gd + sizeof(gd_t));
86*4882a593Smuzhiyun memset(bd, 0, sizeof(bd_t));
87*4882a593Smuzhiyun gd->bd = bd;
88*4882a593Smuzhiyun bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
89*4882a593Smuzhiyun bd->bi_memsize = CONFIG_SYS_L3_SIZE;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun arch_cpu_init();
92*4882a593Smuzhiyun get_clocks();
93*4882a593Smuzhiyun mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
94*4882a593Smuzhiyun CONFIG_SPL_RELOC_MALLOC_SIZE);
95*4882a593Smuzhiyun gd->flags |= GD_FLG_FULL_MALLOC_INIT;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #ifndef CONFIG_SPL_NAND_BOOT
98*4882a593Smuzhiyun env_init();
99*4882a593Smuzhiyun env_relocate();
100*4882a593Smuzhiyun #else
101*4882a593Smuzhiyun /* relocate environment function pointers etc. */
102*4882a593Smuzhiyun nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
103*4882a593Smuzhiyun (uchar *)CONFIG_ENV_ADDR);
104*4882a593Smuzhiyun gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
105*4882a593Smuzhiyun gd->env_valid = ENV_VALID;
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun i2c_init_all();
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun puts("\n\n");
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun dram_init();
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun #ifdef CONFIG_SPL_NAND_BOOT
115*4882a593Smuzhiyun nand_boot();
116*4882a593Smuzhiyun #endif
117*4882a593Smuzhiyun }
118