1*4882a593Smuzhiyun#PBI commands 2*4882a593Smuzhiyun#Initialize CPC1 3*4882a593Smuzhiyun09010000 00200400 4*4882a593Smuzhiyun09138000 00000000 5*4882a593Smuzhiyun091380c0 00000100 6*4882a593Smuzhiyun#Configure CPC1 as 512KB SRAM 7*4882a593Smuzhiyun09010100 00000000 8*4882a593Smuzhiyun09010104 fff80009 9*4882a593Smuzhiyun09010f00 08000000 10*4882a593Smuzhiyun09010000 80000000 11*4882a593Smuzhiyun#Configure LAW for CPC1 12*4882a593Smuzhiyun09000d00 00000000 13*4882a593Smuzhiyun09000d04 fff80000 14*4882a593Smuzhiyun09000d08 81000012 15*4882a593Smuzhiyun#Configure alternate space 16*4882a593Smuzhiyun09000010 00000000 17*4882a593Smuzhiyun09000014 ff000000 18*4882a593Smuzhiyun09000018 81000000 19*4882a593Smuzhiyun#Configure SPI controller 20*4882a593Smuzhiyun09110000 80000403 21*4882a593Smuzhiyun09110020 2d170008 22*4882a593Smuzhiyun09110024 00100008 23*4882a593Smuzhiyun09110028 00100008 24*4882a593Smuzhiyun0911002c 00100008 25*4882a593Smuzhiyun#slowing down the MDC clock to make it <= 2.5 MHZ 26*4882a593Smuzhiyun094fc030 00008148 27*4882a593Smuzhiyun094fd030 00008148 28*4882a593Smuzhiyun#Flush PBL data 29*4882a593Smuzhiyun09138000 00000000 30*4882a593Smuzhiyun091380c0 00000000 31