1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __B4860QDS_QIXIS_H__ 8*4882a593Smuzhiyun #define __B4860QDS_QIXIS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Definitions of QIXIS Registers for B4860QDS */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* BRDCFG4[4:7]] select EC1 and EC2 as a pair */ 13*4882a593Smuzhiyun #define BRDCFG4_EMISEL_MASK 0xE0 14*4882a593Smuzhiyun #define BRDCFG4_EMISEL_SHIFT 5 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* CLK */ 17*4882a593Smuzhiyun #define QIXIS_CLK_66 0x0 18*4882a593Smuzhiyun #define QIXIS_CLK_100 0x1 19*4882a593Smuzhiyun #define QIXIS_CLK_125 0x2 20*4882a593Smuzhiyun #define QIXIS_CLK_133 0x3 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define QIXIS_SRDS1CLK_122 0x5a 23*4882a593Smuzhiyun #define QIXIS_SRDS1CLK_125 0x5e 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* SGMII */ 26*4882a593Smuzhiyun #define PHY_BASE_ADDR 0x18 27*4882a593Smuzhiyun #define PORT_NUM 0x04 28*4882a593Smuzhiyun #define REGNUM 0x00 29*4882a593Smuzhiyun #endif 30