1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __CROSSBAR_CONNECTIONS_H__ 8*4882a593Smuzhiyun #define __CROSSBAR_CONNECTIONS_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define NUM_CON_VSC3316 8 11*4882a593Smuzhiyun #define NUM_CON_VSC3308 4 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10}, 14*4882a593Smuzhiyun {5, 11}, {4, 5}, {2, 6}, {12, 9} }; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0}, 17*4882a593Smuzhiyun {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1}, 20*4882a593Smuzhiyun {7, 8}, {9, 0}, {2, 14}, {12, 15}, 21*4882a593Smuzhiyun {-1, -1}, {-1, -1} }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1}, 24*4882a593Smuzhiyun {7, 8}, {9, 0}, {5, 14}, {4, 15}, 25*4882a593Smuzhiyun {-1, -1}, {-1, -1} }; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1}, 28*4882a593Smuzhiyun {7, 8}, {9, 0}, {5, 14}, 29*4882a593Smuzhiyun {4, 15}, {2, 12}, {12, 13} }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef CONFIG_ARCH_B4420 32*4882a593Smuzhiyun static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15}, 33*4882a593Smuzhiyun {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 34*4882a593Smuzhiyun #endif 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1}, 37*4882a593Smuzhiyun {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9}, 40*4882a593Smuzhiyun {11, 11}, {5, 10}, {6, 3}, {9, 12} }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9}, 43*4882a593Smuzhiyun {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1}, 46*4882a593Smuzhiyun {7, 8}, {1, 9}, {14, 3}, {15, 12}, 47*4882a593Smuzhiyun {-1, -1}, {-1, -1} }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1}, 50*4882a593Smuzhiyun {7, 8}, {1, 9}, {14, 11}, {15, 10}, 51*4882a593Smuzhiyun {-1, -1}, {-1, -1} }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1}, 54*4882a593Smuzhiyun {7, 8}, {1, 9}, {14, 11}, 55*4882a593Smuzhiyun {15, 10}, {13, 3}, {12, 12} }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #ifdef CONFIG_ARCH_B4420 58*4882a593Smuzhiyun static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10}, 59*4882a593Smuzhiyun {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 60*4882a593Smuzhiyun #endif 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1}, 63*4882a593Smuzhiyun {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif 74