1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2020 Rockchip Electronics Co., Ltd
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <dwc3-uboot.h>
10*4882a593Smuzhiyun #include <usb.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
13*4882a593Smuzhiyun
rk_board_init(void)14*4882a593Smuzhiyun int rk_board_init(void)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_ROCKCHIP_DMC_FSP)
17*4882a593Smuzhiyun u32 ret = 0;
18*4882a593Smuzhiyun struct udevice *dev;
19*4882a593Smuzhiyun ret = uclass_get_device_by_driver(UCLASS_DMC, DM_GET_DRIVER(dmc_fsp), &dev);
20*4882a593Smuzhiyun if (ret) {
21*4882a593Smuzhiyun printf("dmc_fsp failed, ret=%d\n", ret);
22*4882a593Smuzhiyun return 0;
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun #endif
25*4882a593Smuzhiyun return 0;
26*4882a593Smuzhiyun }
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #ifdef CONFIG_USB_DWC3
29*4882a593Smuzhiyun static struct dwc3_device dwc3_device_data = {
30*4882a593Smuzhiyun .maximum_speed = USB_SPEED_HIGH,
31*4882a593Smuzhiyun .base = 0xfcc00000,
32*4882a593Smuzhiyun .dr_mode = USB_DR_MODE_PERIPHERAL,
33*4882a593Smuzhiyun .index = 0,
34*4882a593Smuzhiyun .dis_u2_susphy_quirk = 1,
35*4882a593Smuzhiyun .usb2_phyif_utmi_width = 16,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
usb_gadget_handle_interrupts(void)38*4882a593Smuzhiyun int usb_gadget_handle_interrupts(void)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun dwc3_uboot_handle_interrupt(0);
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
board_usb_init(int index,enum usb_init_type init)44*4882a593Smuzhiyun int board_usb_init(int index, enum usb_init_type init)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun return dwc3_uboot_init(&dwc3_device_data);
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun #endif
49