1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2009 Renesas Solutions Corp. 3*4882a593Smuzhiyun * Copyright (C) 2009 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * board/espt/lowlevel_init.S 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun#include <config.h> 11*4882a593Smuzhiyun#include <asm/processor.h> 12*4882a593Smuzhiyun#include <asm/macro.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun .global lowlevel_init 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun .text 17*4882a593Smuzhiyun .align 2 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunlowlevel_init: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun write32 WDTCSR_A, WDTCSR_D 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun write32 WDTST_A, WDTST_D 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun write32 WDTBST_A, WDTBST_D 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun write32 CCR_A, CCR_CACHE_ICI_D 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun write32 MMUCR_A, MMU_CONTROL_TI_D 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun write32 MSTPCR0_A, MSTPCR0_D 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun write32 MSTPCR1_A, MSTPCR1_D 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun write32 RAMCR_A, RAMCR_D 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* 38*4882a593Smuzhiyun * Setting infomation from 39*4882a593Smuzhiyun * original ESPT-GIGA bootloader register 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun write32 MMSEL_A, MMSEL_D 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* dummy */ 44*4882a593Smuzhiyun mov.l @r1, r2 45*4882a593Smuzhiyun mov.l @r1, r2 46*4882a593Smuzhiyun synco 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun write32 BCR_A, BCR_D 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun write32 CS0BCR_A, CS0BCR_D 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun write32 CS0WCR_A, CS0WCR_D 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * DDR-SDRAM setting 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* set DDR-SDRAM dummy read */ 59*4882a593Smuzhiyun write32 MMSEL_A, MMSEL_D 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun write32 MMSEL_A, CS0_A 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* set DDR-SDRAM bus/endian etc */ 64*4882a593Smuzhiyun write32 MIM_U_A, MIM_U_D 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun write32 MIM_L_A, MIM_L_D0 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun write32 SDR_L_A, SDR_L_A_D0 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun write32 STR_L_A, STR_L_A_D0 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* DDR-SDRAM access control */ 73*4882a593Smuzhiyun write32 MIM_L_A, MIM_L_D1 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun write32 SCR_L_A, SCR_L_A_D0 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun write32 SCR_L_A, SCR_L_A_D1 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun write32 EMRS_A, EMRS_D 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun write32 MRS1_A, MRS1_D 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun write32 MIM_U_A, MIM_U_D 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun write32 MIM_L_A, MIM_L_A_D2 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun write32 SCR_L_A, SCR_L_A_D2 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun write32 SCR_L_A, SCR_L_A_D2 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun write32 MRS2_A, MRS2_D 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* wait 200us */ 94*4882a593Smuzhiyun wait_timer REPEAT_R3 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* GPIO setting */ 97*4882a593Smuzhiyun write16 PSEL0_A, PSEL0_D 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun write16 PSEL1_A, PSEL1_D 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun write16 PSEL2_A, PSEL2_D 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun write16 PSEL3_A, PSEL3_D 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun write16 PSEL4_A, PSEL4_D 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun write8 PADR_A, PADR_D 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun write16 PACR_A, PACR_D 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun write8 PBDR_A, PBDR_D 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun write16 PBCR_A, PBCR_D 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun write8 PCDR_A, PCDR_D 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun write16 PCCR_A, PCCR_D 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun write8 PDDR_A, PDDR_D 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun write16 PDCR_A, PDCR_D 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun write16 PECR_A, PECR_D 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun write16 PFCR_A, PFCR_D 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun write16 PGCR_A, PGCR_D 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun write16 PHCR_A, PHCR_D 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun write16 PICR_A, PICR_D 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun write8 PJDR_A, PJDR_D 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun write16 PJCR_A, PJCR_D 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* wait 50us */ 138*4882a593Smuzhiyun wait_timer REPEAT_R3 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun write8 PKDR_A, PKDR_D 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun write16 PKCR_A, PKCR_D 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun write16 PLCR_A, PLCR_D 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun write16 PMCR_A, PMCR_D 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun write16 PNCR_A, PNCR_D 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun write16 POCR_A, POCR_D 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* ICR0 ,ICR1 */ 154*4882a593Smuzhiyun write32 ICR0_A, ICR0_D 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun write32 ICR1_A, ICR1_D 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun /* USB Host */ 159*4882a593Smuzhiyun write32 USB_USBHSC_A, USB_USBHSC_D 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun write32 CCR_A, CCR_CACHE_D_2 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun rts 164*4882a593Smuzhiyun nop 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun .align 2 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun/* GPIO Crontrol Register */ 169*4882a593SmuzhiyunPACR_A: .long 0xFFEF0000 170*4882a593SmuzhiyunPBCR_A: .long 0xFFEF0002 171*4882a593SmuzhiyunPCCR_A: .long 0xFFEF0004 172*4882a593SmuzhiyunPDCR_A: .long 0xFFEF0006 173*4882a593SmuzhiyunPECR_A: .long 0xFFEF0008 174*4882a593SmuzhiyunPFCR_A: .long 0xFFEF000A 175*4882a593SmuzhiyunPGCR_A: .long 0xFFEF000C 176*4882a593SmuzhiyunPHCR_A: .long 0xFFEF000E 177*4882a593SmuzhiyunPICR_A: .long 0xFFEF0010 178*4882a593SmuzhiyunPJCR_A: .long 0xFFEF0012 179*4882a593SmuzhiyunPKCR_A: .long 0xFFEF0014 180*4882a593SmuzhiyunPLCR_A: .long 0xFFEF0016 181*4882a593SmuzhiyunPMCR_A: .long 0xFFEF0018 182*4882a593SmuzhiyunPNCR_A: .long 0xFFEF001A 183*4882a593SmuzhiyunPOCR_A: .long 0xFFEF001C 184*4882a593Smuzhiyun 185*4882a593Smuzhiyun/* GPIO Data Register */ 186*4882a593SmuzhiyunPADR_A: .long 0xFFEF0020 187*4882a593SmuzhiyunPBDR_A: .long 0xFFEF0022 188*4882a593SmuzhiyunPCDR_A: .long 0xFFEF0024 189*4882a593SmuzhiyunPDDR_A: .long 0xFFEF0026 190*4882a593SmuzhiyunPJDR_A: .long 0xFFEF0032 191*4882a593SmuzhiyunPKDR_A: .long 0xFFEF0034 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun/* GPIO Set data */ 194*4882a593SmuzhiyunPADR_D: .long 0x00000000 195*4882a593SmuzhiyunPACR_D: .word 0x1400 196*4882a593Smuzhiyun.align 2 197*4882a593SmuzhiyunPBDR_D: .long 0x00000000 198*4882a593SmuzhiyunPBCR_D: .word 0x555A 199*4882a593Smuzhiyun.align 2 200*4882a593SmuzhiyunPCDR_D: .long 0x00000000 201*4882a593SmuzhiyunPCCR_D: .word 0x5555 202*4882a593Smuzhiyun.align 2 203*4882a593SmuzhiyunPDDR_D: .long 0x00000000 204*4882a593SmuzhiyunPDCR_D: .word 0x0155 205*4882a593SmuzhiyunPECR_D: .word 0x0000 206*4882a593SmuzhiyunPFCR_D: .word 0x0000 207*4882a593SmuzhiyunPGCR_D: .word 0x0000 208*4882a593SmuzhiyunPHCR_D: .word 0x0000 209*4882a593SmuzhiyunPICR_D: .word 0x0800 210*4882a593SmuzhiyunPJDR_D: .long 0x00000006 211*4882a593SmuzhiyunPJCR_D: .word 0x5A57 212*4882a593Smuzhiyun.align 2 213*4882a593SmuzhiyunPKDR_D: .long 0x00000000 214*4882a593SmuzhiyunPKCR_D: .word 0xFFF9 215*4882a593Smuzhiyun.align 2 216*4882a593SmuzhiyunPLCR_D: .word 0xC330 217*4882a593SmuzhiyunPMCR_D: .word 0xFFFF 218*4882a593SmuzhiyunPNCR_D: .word 0x0242 219*4882a593SmuzhiyunPOCR_D: .word 0x0000 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun/* Pin Select */ 222*4882a593SmuzhiyunPSEL0_A: .long 0xFFEF0070 223*4882a593SmuzhiyunPSEL1_A: .long 0xFFEF0072 224*4882a593SmuzhiyunPSEL2_A: .long 0xFFEF0074 225*4882a593SmuzhiyunPSEL3_A: .long 0xFFEF0076 226*4882a593SmuzhiyunPSEL4_A: .long 0xFFEF0078 227*4882a593SmuzhiyunPSEL0_D: .word 0x0001 228*4882a593SmuzhiyunPSEL1_D: .word 0x2400 229*4882a593SmuzhiyunPSEL2_D: .word 0x0000 230*4882a593SmuzhiyunPSEL3_D: .word 0x2421 231*4882a593SmuzhiyunPSEL4_D: .word 0x0000 232*4882a593Smuzhiyun.align 2 233*4882a593Smuzhiyun 234*4882a593SmuzhiyunMMSEL_A: .long 0xFE600020 235*4882a593SmuzhiyunBCR_A: .long 0xFF801000 236*4882a593SmuzhiyunCS0BCR_A: .long 0xFF802000 237*4882a593SmuzhiyunCS0WCR_A: .long 0xFF802008 238*4882a593SmuzhiyunICR0_A: .long 0xFFD00000 239*4882a593SmuzhiyunICR1_A: .long 0xFFD0001C 240*4882a593Smuzhiyun 241*4882a593SmuzhiyunMMSEL_D: .long 0xA5A50000 242*4882a593SmuzhiyunBCR_D: .long 0x05000000 243*4882a593SmuzhiyunCS0BCR_D: .long 0x232306F0 244*4882a593SmuzhiyunCS0WCR_D: .long 0x00011104 245*4882a593SmuzhiyunICR0_D: .long 0x80C00000 246*4882a593SmuzhiyunICR1_D: .long 0x00020000 247*4882a593Smuzhiyun 248*4882a593Smuzhiyun/* RWBT Address */ 249*4882a593SmuzhiyunWDTST_A: .long 0xFFCC0000 250*4882a593SmuzhiyunWDTCSR_A: .long 0xFFCC0004 251*4882a593SmuzhiyunWDTBST_A: .long 0xFFCC0008 252*4882a593Smuzhiyun/* RWBT Data */ 253*4882a593SmuzhiyunWDTST_D: .long 0x5A000FFF 254*4882a593SmuzhiyunWDTCSR_D: .long 0xA5000000 255*4882a593SmuzhiyunWDTBST_D: .long 0x55000000 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun/* Cache Address */ 258*4882a593SmuzhiyunCCR_A: .long 0xFF00001C 259*4882a593SmuzhiyunMMUCR_A: .long 0xFF000010 260*4882a593SmuzhiyunRAMCR_A: .long 0xFF000074 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun/* Cache Data */ 263*4882a593SmuzhiyunCCR_CACHE_ICI_D:.long 0x00000800 264*4882a593SmuzhiyunCCR_CACHE_D_2: .long 0x00000103 265*4882a593SmuzhiyunMMU_CONTROL_TI_D:.long 0x00000004 266*4882a593SmuzhiyunRAMCR_D: .long 0x00000200 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun/* Low power mode control Address */ 269*4882a593SmuzhiyunMSTPCR0_A: .long 0xFFC80030 270*4882a593SmuzhiyunMSTPCR1_A: .long 0xFFC80038 271*4882a593Smuzhiyun/* Low power mode control Data */ 272*4882a593SmuzhiyunMSTPCR0_D: .long 0x00000000 273*4882a593SmuzhiyunMSTPCR1_D: .long 0x00000000 274*4882a593Smuzhiyun 275*4882a593SmuzhiyunREPEAT0_R3: .long 0x00002000 276*4882a593SmuzhiyunREPEAT_R3: .long 0x00000200 277*4882a593SmuzhiyunCS0_A: .long 0xA8000000 278*4882a593Smuzhiyun 279*4882a593SmuzhiyunMIM_U_A: .long 0xFE800008 280*4882a593SmuzhiyunMIM_L_A: .long 0xFE80000C 281*4882a593SmuzhiyunSCR_U_A: .long 0xFE800010 282*4882a593SmuzhiyunSCR_L_A: .long 0xFE800014 283*4882a593SmuzhiyunSTR_U_A: .long 0xFE800018 284*4882a593SmuzhiyunSTR_L_A: .long 0xFE80001C 285*4882a593SmuzhiyunSDR_U_A: .long 0xFE800030 286*4882a593SmuzhiyunSDR_L_A: .long 0xFE800034 287*4882a593SmuzhiyunEMRS_A: .long 0xFE902000 288*4882a593SmuzhiyunMRS1_A: .long 0xFE900B08 289*4882a593SmuzhiyunMRS2_A: .long 0xFE900308 290*4882a593Smuzhiyun 291*4882a593SmuzhiyunMIM_U_D: .long 0x00000000 292*4882a593SmuzhiyunMIM_L_D0: .long 0x04100008 293*4882a593SmuzhiyunMIM_L_D1: .long 0x02EE0009 294*4882a593SmuzhiyunMIM_L_D2: .long 0x02EE0209 295*4882a593Smuzhiyun 296*4882a593SmuzhiyunSDR_L_A_D0: .long 0x00000300 297*4882a593SmuzhiyunSTR_L_A_D0: .long 0x00010040 298*4882a593SmuzhiyunMIM_L_A_D1: .long 0x04100009 299*4882a593SmuzhiyunSCR_L_A_D0: .long 0x00000003 300*4882a593SmuzhiyunSCR_L_A_D1: .long 0x00000002 301*4882a593SmuzhiyunMIM_L_A_D2: .long 0x04100209 302*4882a593SmuzhiyunSCR_L_A_D2: .long 0x00000004 303*4882a593Smuzhiyun 304*4882a593SmuzhiyunSCR_L_NORMAL: .long 0x00000000 305*4882a593SmuzhiyunSCR_L_NOP: .long 0x00000001 306*4882a593SmuzhiyunSCR_L_PALL: .long 0x00000002 307*4882a593SmuzhiyunSCR_L_CKE_EN: .long 0x00000003 308*4882a593SmuzhiyunSCR_L_CBR: .long 0x00000004 309*4882a593Smuzhiyun 310*4882a593SmuzhiyunSTR_L_D: .long 0x000F3980 311*4882a593SmuzhiyunSDR_L_D: .long 0x00000400 312*4882a593SmuzhiyunEMRS_D: .long 0x00000000 313*4882a593SmuzhiyunMRS1_D: .long 0x00000000 314*4882a593SmuzhiyunMRS2_D: .long 0x00000000 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun/* USB */ 317*4882a593SmuzhiyunUSB_USBHSC_A: .long 0xFFEC80F0 318*4882a593SmuzhiyunUSB_USBHSC_D: .long 0x00000000 319