1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * pci.c -- esd VME8349 PCI board support.
3*4882a593Smuzhiyun * Copyright (c) 2006 Wind River Systems, Inc.
4*4882a593Smuzhiyun * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
5*4882a593Smuzhiyun * Copyright (c) 2009 esd gmbh.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Reinhard Arlt <reinhard.arlt@esd-electronics.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Based on MPC8349 PCI support but w/o PIB related code.
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <asm/mmu.h>
15*4882a593Smuzhiyun #include <asm/io.h>
16*4882a593Smuzhiyun #include <common.h>
17*4882a593Smuzhiyun #include <mpc83xx.h>
18*4882a593Smuzhiyun #include <pci.h>
19*4882a593Smuzhiyun #include <i2c.h>
20*4882a593Smuzhiyun #include <asm/fsl_i2c.h>
21*4882a593Smuzhiyun #include "vme8349pin.h"
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static struct pci_region pci1_regions[] = {
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MEM_BASE,
28*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
29*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MEM_SIZE,
30*4882a593Smuzhiyun flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
31*4882a593Smuzhiyun },
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_IO_BASE,
34*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_IO_PHYS,
35*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_IO_SIZE,
36*4882a593Smuzhiyun flags: PCI_REGION_IO
37*4882a593Smuzhiyun },
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
40*4882a593Smuzhiyun phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
41*4882a593Smuzhiyun size: CONFIG_SYS_PCI1_MMIO_SIZE,
42*4882a593Smuzhiyun flags: PCI_REGION_MEM
43*4882a593Smuzhiyun },
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /*
47*4882a593Smuzhiyun * pci_init_board()
48*4882a593Smuzhiyun *
49*4882a593Smuzhiyun * NOTICE: PCI2 is not supported. There is only one
50*4882a593Smuzhiyun * physical PCI slot on the board.
51*4882a593Smuzhiyun *
52*4882a593Smuzhiyun */
53*4882a593Smuzhiyun void
pci_init_board(void)54*4882a593Smuzhiyun pci_init_board(void)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
57*4882a593Smuzhiyun volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
58*4882a593Smuzhiyun volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
59*4882a593Smuzhiyun struct pci_region *reg[] = { pci1_regions };
60*4882a593Smuzhiyun u8 reg8;
61*4882a593Smuzhiyun int monarch = 0;
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun i2c_set_bus_num(1);
64*4882a593Smuzhiyun /* Read the PCI_M66EN jumper setting */
65*4882a593Smuzhiyun if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, ®8, 1) == 0) ||
66*4882a593Smuzhiyun (i2c_read(0x38 , 0, 0, ®8, 1) == 0)) {
67*4882a593Smuzhiyun if (reg8 & 0x40) {
68*4882a593Smuzhiyun clk->occr = 0xff000000; /* 66 MHz PCI */
69*4882a593Smuzhiyun printf("PCI: 66MHz\n");
70*4882a593Smuzhiyun } else {
71*4882a593Smuzhiyun clk->occr = 0xffff0003; /* 33 MHz PCI */
72*4882a593Smuzhiyun printf("PCI: 33MHz\n");
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun if (((reg8 & 0x01) == 0) || ((reg8 & 0x02) == 0))
75*4882a593Smuzhiyun monarch = 1;
76*4882a593Smuzhiyun } else {
77*4882a593Smuzhiyun clk->occr = 0xffff0003; /* 33 MHz PCI */
78*4882a593Smuzhiyun printf("PCI: 33MHz (I2C read failed)\n");
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun udelay(2000);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Assert/deassert VME reset
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun clrsetbits_be32(&immr->gpio[1].dat,
86*4882a593Smuzhiyun GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
87*4882a593Smuzhiyun GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
88*4882a593Smuzhiyun setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
89*4882a593Smuzhiyun GPIO2_TSI_POWERUP_RESET_N |
90*4882a593Smuzhiyun GPIO2_VME_RESET_N |
91*4882a593Smuzhiyun GPIO2_L_RESET_EN_N);
92*4882a593Smuzhiyun clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
93*4882a593Smuzhiyun udelay(200);
94*4882a593Smuzhiyun setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
95*4882a593Smuzhiyun udelay(200);
96*4882a593Smuzhiyun setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
97*4882a593Smuzhiyun udelay(600000);
98*4882a593Smuzhiyun clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* Configure PCI Local Access Windows */
101*4882a593Smuzhiyun pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
102*4882a593Smuzhiyun pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
105*4882a593Smuzhiyun pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun udelay(2000);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (monarch == 0) {
110*4882a593Smuzhiyun mpc83xx_pci_init(1, reg);
111*4882a593Smuzhiyun } else {
112*4882a593Smuzhiyun /*
113*4882a593Smuzhiyun * Release PCI RST Output signal
114*4882a593Smuzhiyun */
115*4882a593Smuzhiyun out_be32(&immr->pci_ctrl[0].gcr, 0);
116*4882a593Smuzhiyun udelay(2000);
117*4882a593Smuzhiyun out_be32(&immr->pci_ctrl[0].gcr, 1);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun }
120