1*4882a593Smuzhiyun/* Memory sub-system initialization code */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun#include <config.h> 4*4882a593Smuzhiyun#include <mach/au1x00.h> 5*4882a593Smuzhiyun#include <asm/regdef.h> 6*4882a593Smuzhiyun#include <asm/mipsregs.h> 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun#define AU1500_SYS_ADDR 0xB1900000 9*4882a593Smuzhiyun#define sys_endian 0x0038 10*4882a593Smuzhiyun#define CP0_Config0 $16 11*4882a593Smuzhiyun#define CPU_SCALE ((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */ 12*4882a593Smuzhiyun#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun .text 15*4882a593Smuzhiyun .set noreorder 16*4882a593Smuzhiyun .set mips32 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun .globl lowlevel_init 19*4882a593Smuzhiyunlowlevel_init: 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Step 1) Establish CPU endian mode. 22*4882a593Smuzhiyun * Db1500-specific: 23*4882a593Smuzhiyun * Switch S1.1 Off(bit7 reads 1) is Little Endian 24*4882a593Smuzhiyun * Switch S1.1 On (bit7 reads 0) is Big Endian 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun#ifdef CONFIG_DBAU1550 27*4882a593Smuzhiyun li t0, MEM_STCFG2 28*4882a593Smuzhiyun li t1, 0x00000040 29*4882a593Smuzhiyun sw t1, 0(t0) 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun li t0, MEM_STTIME2 32*4882a593Smuzhiyun li t1, 0x22080a20 33*4882a593Smuzhiyun sw t1, 0(t0) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun li t0, MEM_STADDR2 36*4882a593Smuzhiyun li t1, 0x10c03f00 37*4882a593Smuzhiyun sw t1, 0(t0) 38*4882a593Smuzhiyun#else 39*4882a593Smuzhiyun li t0, MEM_STCFG1 40*4882a593Smuzhiyun li t1, 0x00000080 41*4882a593Smuzhiyun sw t1, 0(t0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun li t0, MEM_STTIME1 44*4882a593Smuzhiyun li t1, 0x22080a20 45*4882a593Smuzhiyun sw t1, 0(t0) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun li t0, MEM_STADDR1 48*4882a593Smuzhiyun li t1, 0x10c03f00 49*4882a593Smuzhiyun sw t1, 0(t0) 50*4882a593Smuzhiyun#endif 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun li t0, DB1XX0_BCSR_ADDR 53*4882a593Smuzhiyun lw t1,8(t0) 54*4882a593Smuzhiyun andi t1,t1,0x80 55*4882a593Smuzhiyun beq zero,t1,big_endian 56*4882a593Smuzhiyun nop 57*4882a593Smuzhiyunlittle_endian: 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Change Au1 core to little endian */ 60*4882a593Smuzhiyun li t0, AU1500_SYS_ADDR 61*4882a593Smuzhiyun li t1, 1 62*4882a593Smuzhiyun sw t1, sys_endian(t0) 63*4882a593Smuzhiyun mfc0 t2, CP0_CONFIG 64*4882a593Smuzhiyun mtc0 t2, CP0_CONFIG 65*4882a593Smuzhiyun nop 66*4882a593Smuzhiyun nop 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* Big Endian is default so nothing to do but fall through */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyunbig_endian: 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* 73*4882a593Smuzhiyun * Step 2) Establish Status Register 74*4882a593Smuzhiyun * (set BEV, clear ERL, clear EXL, clear IE) 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun li t1, 0x00400000 77*4882a593Smuzhiyun mtc0 t1, CP0_STATUS 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* 80*4882a593Smuzhiyun * Step 3) Establish CP0 Config0 81*4882a593Smuzhiyun * (set OD, set K0=3) 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun li t1, 0x00080003 84*4882a593Smuzhiyun mtc0 t1, CP0_CONFIG 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* 87*4882a593Smuzhiyun * Step 4) Disable Watchpoint facilities 88*4882a593Smuzhiyun */ 89*4882a593Smuzhiyun li t1, 0x00000000 90*4882a593Smuzhiyun mtc0 t1, CP0_WATCHLO 91*4882a593Smuzhiyun mtc0 t1, CP0_IWATCHLO 92*4882a593Smuzhiyun /* 93*4882a593Smuzhiyun * Step 5) Disable the performance counters 94*4882a593Smuzhiyun */ 95*4882a593Smuzhiyun mtc0 zero, CP0_PERFORMANCE 96*4882a593Smuzhiyun nop 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* 99*4882a593Smuzhiyun * Step 6) Establish EJTAG Debug register 100*4882a593Smuzhiyun */ 101*4882a593Smuzhiyun mtc0 zero, CP0_DEBUG 102*4882a593Smuzhiyun nop 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* 105*4882a593Smuzhiyun * Step 7) Establish Cause 106*4882a593Smuzhiyun * (set IV bit) 107*4882a593Smuzhiyun */ 108*4882a593Smuzhiyun li t1, 0x00800000 109*4882a593Smuzhiyun mtc0 t1, CP0_CAUSE 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Establish Wired (and Random) */ 112*4882a593Smuzhiyun mtc0 zero, CP0_WIRED 113*4882a593Smuzhiyun nop 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun#ifdef CONFIG_DBAU1550 116*4882a593Smuzhiyun /* No workaround if running from ram */ 117*4882a593Smuzhiyun lui t0, 0xffc0 118*4882a593Smuzhiyun lui t3, 0xbfc0 119*4882a593Smuzhiyun and t1, ra, t0 120*4882a593Smuzhiyun bne t1, t3, noCacheJump 121*4882a593Smuzhiyun nop 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /*** From AMD YAMON ***/ 124*4882a593Smuzhiyun /* 125*4882a593Smuzhiyun * Step 8) Initialize the caches 126*4882a593Smuzhiyun */ 127*4882a593Smuzhiyun li t0, (16*1024) 128*4882a593Smuzhiyun li t1, 32 129*4882a593Smuzhiyun li t2, 0x80000000 130*4882a593Smuzhiyun addu t3, t0, t2 131*4882a593Smuzhiyuncacheloop: 132*4882a593Smuzhiyun cache 0, 0(t2) 133*4882a593Smuzhiyun cache 1, 0(t2) 134*4882a593Smuzhiyun addu t2, t1 135*4882a593Smuzhiyun bne t2, t3, cacheloop 136*4882a593Smuzhiyun nop 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* Save return address */ 139*4882a593Smuzhiyun move t3, ra 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* Run from cacheable space now */ 142*4882a593Smuzhiyun bal cachehere 143*4882a593Smuzhiyun nop 144*4882a593Smuzhiyuncachehere: 145*4882a593Smuzhiyun li t1, ~0x20000000 /* convert to KSEG0 */ 146*4882a593Smuzhiyun and t0, ra, t1 147*4882a593Smuzhiyun addi t0, 5*4 /* 5 insns beyond cachehere */ 148*4882a593Smuzhiyun jr t0 149*4882a593Smuzhiyun nop 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun /* Restore return address */ 152*4882a593Smuzhiyun move ra, t3 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* 155*4882a593Smuzhiyun * Step 9) Initialize the TLB 156*4882a593Smuzhiyun */ 157*4882a593Smuzhiyun li t0, 0 # index value 158*4882a593Smuzhiyun li t1, 0x00000000 # entryhi value 159*4882a593Smuzhiyun li t2, 32 # 32 entries 160*4882a593Smuzhiyun 161*4882a593Smuzhiyuntlbloop: 162*4882a593Smuzhiyun /* Probe TLB for matching EntryHi */ 163*4882a593Smuzhiyun mtc0 t1, CP0_ENTRYHI 164*4882a593Smuzhiyun tlbp 165*4882a593Smuzhiyun nop 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* Examine Index[P], 1=no matching entry */ 168*4882a593Smuzhiyun mfc0 t3, CP0_INDEX 169*4882a593Smuzhiyun li t4, 0x80000000 170*4882a593Smuzhiyun and t3, t4, t3 171*4882a593Smuzhiyun addiu t1, t1, 1 # increment t1 (asid) 172*4882a593Smuzhiyun beq zero, t3, tlbloop 173*4882a593Smuzhiyun nop 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun /* Initialize the TLB entry */ 176*4882a593Smuzhiyun mtc0 t0, CP0_INDEX 177*4882a593Smuzhiyun mtc0 zero, CP0_ENTRYLO0 178*4882a593Smuzhiyun mtc0 zero, CP0_ENTRYLO1 179*4882a593Smuzhiyun mtc0 zero, CP0_PAGEMASK 180*4882a593Smuzhiyun tlbwi 181*4882a593Smuzhiyun 182*4882a593Smuzhiyun /* Do it again */ 183*4882a593Smuzhiyun addiu t0, t0, 1 184*4882a593Smuzhiyun bne t0, t2, tlbloop 185*4882a593Smuzhiyun nop 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun#endif /* CONFIG_DBAU1550 */ 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* First setup pll:s to make serial work ok */ 190*4882a593Smuzhiyun /* We have a 12 MHz crystal */ 191*4882a593Smuzhiyun li t0, SYS_CPUPLL 192*4882a593Smuzhiyun li t1, CPU_SCALE /* CPU clock */ 193*4882a593Smuzhiyun sw t1, 0(t0) 194*4882a593Smuzhiyun sync 195*4882a593Smuzhiyun nop 196*4882a593Smuzhiyun nop 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun /* wait 1mS for clocks to settle */ 199*4882a593Smuzhiyun li t1, MEM_1MS 200*4882a593Smuzhiyun1: add t1, -1 201*4882a593Smuzhiyun bne t1, zero, 1b 202*4882a593Smuzhiyun nop 203*4882a593Smuzhiyun /* Setup AUX PLL */ 204*4882a593Smuzhiyun li t0, SYS_AUXPLL 205*4882a593Smuzhiyun li t1, 0x20 /* 96 MHz */ 206*4882a593Smuzhiyun sw t1, 0(t0) /* aux pll */ 207*4882a593Smuzhiyun sync 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun#ifdef CONFIG_DBAU1550 210*4882a593Smuzhiyun /* Static memory controller */ 211*4882a593Smuzhiyun /* RCE0 - can not change while fetching, do so from icache */ 212*4882a593Smuzhiyun move t2, ra /* Store return address */ 213*4882a593Smuzhiyun bal getAddr 214*4882a593Smuzhiyun nop 215*4882a593Smuzhiyun 216*4882a593SmuzhiyungetAddr: 217*4882a593Smuzhiyun move t1, ra 218*4882a593Smuzhiyun move ra, t2 /* Move return addess back */ 219*4882a593Smuzhiyun 220*4882a593Smuzhiyun cache 0x14,0(t1) 221*4882a593Smuzhiyun cache 0x14,32(t1) 222*4882a593Smuzhiyun /*** /From YAMON ***/ 223*4882a593Smuzhiyun 224*4882a593SmuzhiyunnoCacheJump: 225*4882a593Smuzhiyun#endif /* CONFIG_DBAU1550 */ 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun#ifdef CONFIG_DBAU1550 228*4882a593Smuzhiyun li t0, MEM_STTIME0 229*4882a593Smuzhiyun li t1, 0x040181D7 230*4882a593Smuzhiyun sw t1, 0(t0) 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun /* RCE0 AMD MirrorBit Flash (?) */ 233*4882a593Smuzhiyun li t0, MEM_STCFG0 234*4882a593Smuzhiyun li t1, 0x00000003 235*4882a593Smuzhiyun sw t1, 0(t0) 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun li t0, MEM_STADDR0 238*4882a593Smuzhiyun li t1, 0x11803E00 239*4882a593Smuzhiyun sw t1, 0(t0) 240*4882a593Smuzhiyun#else /* CONFIG_DBAU1550 */ 241*4882a593Smuzhiyun li t0, MEM_STTIME0 242*4882a593Smuzhiyun li t1, 0x040181D7 243*4882a593Smuzhiyun sw t1, 0(t0) 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* RCE0 AMD 29LV640M MirrorBit Flash */ 246*4882a593Smuzhiyun li t0, MEM_STCFG0 247*4882a593Smuzhiyun li t1, 0x00000013 248*4882a593Smuzhiyun sw t1, 0(t0) 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun li t0, MEM_STADDR0 251*4882a593Smuzhiyun li t1, 0x11E03F80 252*4882a593Smuzhiyun sw t1, 0(t0) 253*4882a593Smuzhiyun#endif /* CONFIG_DBAU1550 */ 254*4882a593Smuzhiyun 255*4882a593Smuzhiyun /* RCE1 CPLD Board Logic */ 256*4882a593Smuzhiyun li t0, MEM_STCFG1 257*4882a593Smuzhiyun li t1, 0x00000080 258*4882a593Smuzhiyun sw t1, 0(t0) 259*4882a593Smuzhiyun 260*4882a593Smuzhiyun li t0, MEM_STTIME1 261*4882a593Smuzhiyun li t1, 0x22080a20 262*4882a593Smuzhiyun sw t1, 0(t0) 263*4882a593Smuzhiyun 264*4882a593Smuzhiyun li t0, MEM_STADDR1 265*4882a593Smuzhiyun li t1, 0x10c03f00 266*4882a593Smuzhiyun sw t1, 0(t0) 267*4882a593Smuzhiyun 268*4882a593Smuzhiyun#ifdef CONFIG_DBAU1550 269*4882a593Smuzhiyun /* RCE2 CPLD Board Logic */ 270*4882a593Smuzhiyun li t0, MEM_STCFG2 271*4882a593Smuzhiyun li t1, 0x00000040 272*4882a593Smuzhiyun sw t1, 0(t0) 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun li t0, MEM_STTIME2 275*4882a593Smuzhiyun li t1, 0x22080a20 276*4882a593Smuzhiyun sw t1, 0(t0) 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun li t0, MEM_STADDR2 279*4882a593Smuzhiyun li t1, 0x10c03f00 280*4882a593Smuzhiyun sw t1, 0(t0) 281*4882a593Smuzhiyun#else 282*4882a593Smuzhiyun li t0, MEM_STCFG2 283*4882a593Smuzhiyun li t1, 0x00000000 284*4882a593Smuzhiyun sw t1, 0(t0) 285*4882a593Smuzhiyun 286*4882a593Smuzhiyun li t0, MEM_STTIME2 287*4882a593Smuzhiyun li t1, 0x00000000 288*4882a593Smuzhiyun sw t1, 0(t0) 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun li t0, MEM_STADDR2 291*4882a593Smuzhiyun li t1, 0x00000000 292*4882a593Smuzhiyun sw t1, 0(t0) 293*4882a593Smuzhiyun#endif 294*4882a593Smuzhiyun 295*4882a593Smuzhiyun /* RCE3 PCMCIA 250ns */ 296*4882a593Smuzhiyun li t0, MEM_STCFG3 297*4882a593Smuzhiyun li t1, 0x00000002 298*4882a593Smuzhiyun sw t1, 0(t0) 299*4882a593Smuzhiyun 300*4882a593Smuzhiyun li t0, MEM_STTIME3 301*4882a593Smuzhiyun li t1, 0x280E3E07 302*4882a593Smuzhiyun sw t1, 0(t0) 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun li t0, MEM_STADDR3 305*4882a593Smuzhiyun li t1, 0x10000000 306*4882a593Smuzhiyun sw t1, 0(t0) 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun sync 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* Set peripherals to a known state */ 311*4882a593Smuzhiyun li t0, IC0_CFG0CLR 312*4882a593Smuzhiyun li t1, 0xFFFFFFFF 313*4882a593Smuzhiyun sw t1, 0(t0) 314*4882a593Smuzhiyun 315*4882a593Smuzhiyun li t0, IC0_CFG0CLR 316*4882a593Smuzhiyun sw t1, 0(t0) 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun li t0, IC0_CFG1CLR 319*4882a593Smuzhiyun sw t1, 0(t0) 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun li t0, IC0_CFG2CLR 322*4882a593Smuzhiyun sw t1, 0(t0) 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun li t0, IC0_SRCSET 325*4882a593Smuzhiyun sw t1, 0(t0) 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun li t0, IC0_ASSIGNSET 328*4882a593Smuzhiyun sw t1, 0(t0) 329*4882a593Smuzhiyun 330*4882a593Smuzhiyun li t0, IC0_WAKECLR 331*4882a593Smuzhiyun sw t1, 0(t0) 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun li t0, IC0_RISINGCLR 334*4882a593Smuzhiyun sw t1, 0(t0) 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun li t0, IC0_FALLINGCLR 337*4882a593Smuzhiyun sw t1, 0(t0) 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun li t0, IC0_TESTBIT 340*4882a593Smuzhiyun li t1, 0x00000000 341*4882a593Smuzhiyun sw t1, 0(t0) 342*4882a593Smuzhiyun sync 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun li t0, IC1_CFG0CLR 345*4882a593Smuzhiyun li t1, 0xFFFFFFFF 346*4882a593Smuzhiyun sw t1, 0(t0) 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun li t0, IC1_CFG0CLR 349*4882a593Smuzhiyun sw t1, 0(t0) 350*4882a593Smuzhiyun 351*4882a593Smuzhiyun li t0, IC1_CFG1CLR 352*4882a593Smuzhiyun sw t1, 0(t0) 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun li t0, IC1_CFG2CLR 355*4882a593Smuzhiyun sw t1, 0(t0) 356*4882a593Smuzhiyun 357*4882a593Smuzhiyun li t0, IC1_SRCSET 358*4882a593Smuzhiyun sw t1, 0(t0) 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun li t0, IC1_ASSIGNSET 361*4882a593Smuzhiyun sw t1, 0(t0) 362*4882a593Smuzhiyun 363*4882a593Smuzhiyun li t0, IC1_WAKECLR 364*4882a593Smuzhiyun sw t1, 0(t0) 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun li t0, IC1_RISINGCLR 367*4882a593Smuzhiyun sw t1, 0(t0) 368*4882a593Smuzhiyun 369*4882a593Smuzhiyun li t0, IC1_FALLINGCLR 370*4882a593Smuzhiyun sw t1, 0(t0) 371*4882a593Smuzhiyun 372*4882a593Smuzhiyun li t0, IC1_TESTBIT 373*4882a593Smuzhiyun li t1, 0x00000000 374*4882a593Smuzhiyun sw t1, 0(t0) 375*4882a593Smuzhiyun sync 376*4882a593Smuzhiyun 377*4882a593Smuzhiyun li t0, SYS_FREQCTRL0 378*4882a593Smuzhiyun li t1, 0x00000000 379*4882a593Smuzhiyun sw t1, 0(t0) 380*4882a593Smuzhiyun 381*4882a593Smuzhiyun li t0, SYS_FREQCTRL1 382*4882a593Smuzhiyun li t1, 0x00000000 383*4882a593Smuzhiyun sw t1, 0(t0) 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun li t0, SYS_CLKSRC 386*4882a593Smuzhiyun li t1, 0x00000000 387*4882a593Smuzhiyun sw t1, 0(t0) 388*4882a593Smuzhiyun 389*4882a593Smuzhiyun li t0, SYS_PININPUTEN 390*4882a593Smuzhiyun li t1, 0x00000000 391*4882a593Smuzhiyun sw t1, 0(t0) 392*4882a593Smuzhiyun sync 393*4882a593Smuzhiyun 394*4882a593Smuzhiyun li t0, 0xB1100100 395*4882a593Smuzhiyun li t1, 0x00000000 396*4882a593Smuzhiyun sw t1, 0(t0) 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun li t0, 0xB1400100 399*4882a593Smuzhiyun li t1, 0x00000000 400*4882a593Smuzhiyun sw t1, 0(t0) 401*4882a593Smuzhiyun 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun li t0, SYS_WAKEMSK 404*4882a593Smuzhiyun li t1, 0x00000000 405*4882a593Smuzhiyun sw t1, 0(t0) 406*4882a593Smuzhiyun 407*4882a593Smuzhiyun li t0, SYS_WAKESRC 408*4882a593Smuzhiyun li t1, 0x00000000 409*4882a593Smuzhiyun sw t1, 0(t0) 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun /* wait 1mS before setup */ 412*4882a593Smuzhiyun li t1, MEM_1MS 413*4882a593Smuzhiyun1: add t1, -1 414*4882a593Smuzhiyun bne t1, zero, 1b 415*4882a593Smuzhiyun nop 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun#ifdef CONFIG_DBAU1550 418*4882a593Smuzhiyun/* SDCS 0,1,2 DDR SDRAM */ 419*4882a593Smuzhiyun li t0, MEM_SDMODE0 420*4882a593Smuzhiyun li t1, 0x04276221 421*4882a593Smuzhiyun sw t1, 0(t0) 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun li t0, MEM_SDMODE1 424*4882a593Smuzhiyun li t1, 0x04276221 425*4882a593Smuzhiyun sw t1, 0(t0) 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun li t0, MEM_SDMODE2 428*4882a593Smuzhiyun li t1, 0x04276221 429*4882a593Smuzhiyun sw t1, 0(t0) 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun li t0, MEM_SDADDR0 432*4882a593Smuzhiyun li t1, 0xe21003f0 433*4882a593Smuzhiyun sw t1, 0(t0) 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun li t0, MEM_SDADDR1 436*4882a593Smuzhiyun li t1, 0xe21043f0 437*4882a593Smuzhiyun sw t1, 0(t0) 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun li t0, MEM_SDADDR2 440*4882a593Smuzhiyun li t1, 0xe21083f0 441*4882a593Smuzhiyun sw t1, 0(t0) 442*4882a593Smuzhiyun 443*4882a593Smuzhiyun sync 444*4882a593Smuzhiyun 445*4882a593Smuzhiyun li t0, MEM_SDCONFIGA 446*4882a593Smuzhiyun li t1, 0x9030060a /* Program refresh - disabled */ 447*4882a593Smuzhiyun sw t1, 0(t0) 448*4882a593Smuzhiyun sync 449*4882a593Smuzhiyun 450*4882a593Smuzhiyun li t0, MEM_SDCONFIGB 451*4882a593Smuzhiyun li t1, 0x00028000 452*4882a593Smuzhiyun sw t1, 0(t0) 453*4882a593Smuzhiyun sync 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun li t0, MEM_SDPRECMD /* Precharge all */ 456*4882a593Smuzhiyun li t1, 0 457*4882a593Smuzhiyun sw t1, 0(t0) 458*4882a593Smuzhiyun sync 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun li t0, MEM_SDWRMD0 461*4882a593Smuzhiyun li t1, 0x40000000 462*4882a593Smuzhiyun sw t1, 0(t0) 463*4882a593Smuzhiyun sync 464*4882a593Smuzhiyun 465*4882a593Smuzhiyun li t0, MEM_SDWRMD1 466*4882a593Smuzhiyun li t1, 0x40000000 467*4882a593Smuzhiyun sw t1, 0(t0) 468*4882a593Smuzhiyun sync 469*4882a593Smuzhiyun 470*4882a593Smuzhiyun li t0, MEM_SDWRMD2 471*4882a593Smuzhiyun li t1, 0x40000000 472*4882a593Smuzhiyun sw t1, 0(t0) 473*4882a593Smuzhiyun sync 474*4882a593Smuzhiyun 475*4882a593Smuzhiyun li t0, MEM_SDWRMD0 476*4882a593Smuzhiyun li t1, 0x00000063 477*4882a593Smuzhiyun sw t1, 0(t0) 478*4882a593Smuzhiyun sync 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun li t0, MEM_SDWRMD1 481*4882a593Smuzhiyun li t1, 0x00000063 482*4882a593Smuzhiyun sw t1, 0(t0) 483*4882a593Smuzhiyun sync 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun li t0, MEM_SDWRMD2 486*4882a593Smuzhiyun li t1, 0x00000063 487*4882a593Smuzhiyun sw t1, 0(t0) 488*4882a593Smuzhiyun sync 489*4882a593Smuzhiyun 490*4882a593Smuzhiyun li t0, MEM_SDPRECMD /* Precharge all */ 491*4882a593Smuzhiyun sw zero, 0(t0) 492*4882a593Smuzhiyun sync 493*4882a593Smuzhiyun 494*4882a593Smuzhiyun /* Issue 2 autoref */ 495*4882a593Smuzhiyun li t0, MEM_SDAUTOREF 496*4882a593Smuzhiyun sw zero, 0(t0) 497*4882a593Smuzhiyun sync 498*4882a593Smuzhiyun 499*4882a593Smuzhiyun li t0, MEM_SDAUTOREF 500*4882a593Smuzhiyun sw zero, 0(t0) 501*4882a593Smuzhiyun sync 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun /* Enable refresh */ 504*4882a593Smuzhiyun li t0, MEM_SDCONFIGA 505*4882a593Smuzhiyun li t1, 0x9830060a /* Program refresh - enabled */ 506*4882a593Smuzhiyun sw t1, 0(t0) 507*4882a593Smuzhiyun sync 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun#else /* CONFIG_DBAU1550 */ 510*4882a593Smuzhiyun/* SDCS 0,1 SDRAM */ 511*4882a593Smuzhiyun li t0, MEM_SDMODE0 512*4882a593Smuzhiyun li t1, 0x005522AA 513*4882a593Smuzhiyun sw t1, 0(t0) 514*4882a593Smuzhiyun 515*4882a593Smuzhiyun li t0, MEM_SDMODE1 516*4882a593Smuzhiyun li t1, 0x005522AA 517*4882a593Smuzhiyun sw t1, 0(t0) 518*4882a593Smuzhiyun 519*4882a593Smuzhiyun li t0, MEM_SDMODE2 520*4882a593Smuzhiyun li t1, 0x00000000 521*4882a593Smuzhiyun sw t1, 0(t0) 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun li t0, MEM_SDADDR0 524*4882a593Smuzhiyun li t1, 0x001003F8 525*4882a593Smuzhiyun sw t1, 0(t0) 526*4882a593Smuzhiyun 527*4882a593Smuzhiyun 528*4882a593Smuzhiyun li t0, MEM_SDADDR1 529*4882a593Smuzhiyun li t1, 0x001023F8 530*4882a593Smuzhiyun sw t1, 0(t0) 531*4882a593Smuzhiyun 532*4882a593Smuzhiyun li t0, MEM_SDADDR2 533*4882a593Smuzhiyun li t1, 0x00000000 534*4882a593Smuzhiyun sw t1, 0(t0) 535*4882a593Smuzhiyun 536*4882a593Smuzhiyun sync 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun li t0, MEM_SDREFCFG 539*4882a593Smuzhiyun li t1, 0x64000C24 /* Disable */ 540*4882a593Smuzhiyun sw t1, 0(t0) 541*4882a593Smuzhiyun sync 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun li t0, MEM_SDPRECMD 544*4882a593Smuzhiyun sw zero, 0(t0) 545*4882a593Smuzhiyun sync 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun li t0, MEM_SDAUTOREF 548*4882a593Smuzhiyun sw zero, 0(t0) 549*4882a593Smuzhiyun sync 550*4882a593Smuzhiyun sw zero, 0(t0) 551*4882a593Smuzhiyun sync 552*4882a593Smuzhiyun 553*4882a593Smuzhiyun li t0, MEM_SDREFCFG 554*4882a593Smuzhiyun li t1, 0x66000C24 /* Enable */ 555*4882a593Smuzhiyun sw t1, 0(t0) 556*4882a593Smuzhiyun sync 557*4882a593Smuzhiyun 558*4882a593Smuzhiyun li t0, MEM_SDWRMD0 559*4882a593Smuzhiyun li t1, 0x00000033 560*4882a593Smuzhiyun sw t1, 0(t0) 561*4882a593Smuzhiyun sync 562*4882a593Smuzhiyun 563*4882a593Smuzhiyun li t0, MEM_SDWRMD1 564*4882a593Smuzhiyun li t1, 0x00000033 565*4882a593Smuzhiyun sw t1, 0(t0) 566*4882a593Smuzhiyun sync 567*4882a593Smuzhiyun 568*4882a593Smuzhiyun#endif /* CONFIG_DBAU1550 */ 569*4882a593Smuzhiyun /* wait 1mS after setup */ 570*4882a593Smuzhiyun li t1, MEM_1MS 571*4882a593Smuzhiyun1: add t1, -1 572*4882a593Smuzhiyun bne t1, zero, 1b 573*4882a593Smuzhiyun nop 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun li t0, SYS_PINFUNC 576*4882a593Smuzhiyun li t1, 0x00008080 577*4882a593Smuzhiyun sw t1, 0(t0) 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun li t0, SYS_TRIOUTCLR 580*4882a593Smuzhiyun li t1, 0x00001FFF 581*4882a593Smuzhiyun sw t1, 0(t0) 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun li t0, SYS_OUTPUTCLR 584*4882a593Smuzhiyun li t1, 0x00008000 585*4882a593Smuzhiyun sw t1, 0(t0) 586*4882a593Smuzhiyun sync 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun jr ra 589*4882a593Smuzhiyun nop 590