xref: /OK3568_Linux_fs/u-boot/board/davinci/ea20/ea20.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * (C) Copyright 2010
3*4882a593Smuzhiyun  * Stefano Babic, DENX Software Engineering, sbabic@denx.de
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Based on da850evm.c, original Copyrights follow:
6*4882a593Smuzhiyun  *
7*4882a593Smuzhiyun  * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * Based on da830evm.c. Original Copyrights follow:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
12*4882a593Smuzhiyun  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
15*4882a593Smuzhiyun  */
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <common.h>
18*4882a593Smuzhiyun #include <i2c.h>
19*4882a593Smuzhiyun #include <net.h>
20*4882a593Smuzhiyun #include <netdev.h>
21*4882a593Smuzhiyun #include <asm/mach-types.h>
22*4882a593Smuzhiyun #include <asm/arch/hardware.h>
23*4882a593Smuzhiyun #include <asm/ti-common/davinci_nand.h>
24*4882a593Smuzhiyun #include <asm/arch/emac_defs.h>
25*4882a593Smuzhiyun #include <asm/io.h>
26*4882a593Smuzhiyun #include <asm/arch/davinci_misc.h>
27*4882a593Smuzhiyun #include <asm/gpio.h>
28*4882a593Smuzhiyun #include "../../../drivers/video/da8xx-fb.h"
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun static const struct da8xx_panel lcd_panel = {
33*4882a593Smuzhiyun 	/* Casio COM57H531x */
34*4882a593Smuzhiyun 	.name = "Casio_COM57H531x",
35*4882a593Smuzhiyun 	.width = 640,
36*4882a593Smuzhiyun 	.height = 480,
37*4882a593Smuzhiyun 	.hfp = 12,
38*4882a593Smuzhiyun 	.hbp = 144,
39*4882a593Smuzhiyun 	.hsw = 30,
40*4882a593Smuzhiyun 	.vfp = 10,
41*4882a593Smuzhiyun 	.vbp = 35,
42*4882a593Smuzhiyun 	.vsw = 3,
43*4882a593Smuzhiyun 	.pxl_clk = 25000000,
44*4882a593Smuzhiyun 	.invert_pxl_clk = 0,
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun static const struct display_panel disp_panel = {
48*4882a593Smuzhiyun 	QVGA,
49*4882a593Smuzhiyun 	16,
50*4882a593Smuzhiyun 	16,
51*4882a593Smuzhiyun 	COLOR_ACTIVE,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun static const struct lcd_ctrl_config lcd_cfg = {
55*4882a593Smuzhiyun 	&disp_panel,
56*4882a593Smuzhiyun 	.ac_bias		= 255,
57*4882a593Smuzhiyun 	.ac_bias_intrpt		= 0,
58*4882a593Smuzhiyun 	.dma_burst_sz		= 16,
59*4882a593Smuzhiyun 	.bpp			= 16,
60*4882a593Smuzhiyun 	.fdd			= 255,
61*4882a593Smuzhiyun 	.tft_alt_mode		= 0,
62*4882a593Smuzhiyun 	.stn_565_mode		= 0,
63*4882a593Smuzhiyun 	.mono_8bit_mode		= 0,
64*4882a593Smuzhiyun 	.invert_line_clock	= 1,
65*4882a593Smuzhiyun 	.invert_frm_clock	= 1,
66*4882a593Smuzhiyun 	.sync_edge		= 0,
67*4882a593Smuzhiyun 	.sync_ctrl		= 1,
68*4882a593Smuzhiyun 	.raster_order		= 0,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /* SPI0 pin muxer settings */
72*4882a593Smuzhiyun static const struct pinmux_config spi1_pins[] = {
73*4882a593Smuzhiyun 	{ pinmux(5), 1, 1 },
74*4882a593Smuzhiyun 	{ pinmux(5), 1, 2 },
75*4882a593Smuzhiyun 	{ pinmux(5), 1, 4 },
76*4882a593Smuzhiyun 	{ pinmux(5), 1, 5 }
77*4882a593Smuzhiyun };
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun /* I2C pin muxer settings */
80*4882a593Smuzhiyun static const struct pinmux_config i2c_pins[] = {
81*4882a593Smuzhiyun 	{ pinmux(4), 2, 2 },
82*4882a593Smuzhiyun 	{ pinmux(4), 2, 3 }
83*4882a593Smuzhiyun };
84*4882a593Smuzhiyun 
85*4882a593Smuzhiyun /* UART0 pin muxer settings */
86*4882a593Smuzhiyun static const struct pinmux_config uart_pins[] = {
87*4882a593Smuzhiyun 	{ pinmux(3), 2, 7 },
88*4882a593Smuzhiyun 	{ pinmux(3), 2, 6 },
89*4882a593Smuzhiyun 	{ pinmux(3), 2, 4 },
90*4882a593Smuzhiyun 	{ pinmux(3), 2, 5 }
91*4882a593Smuzhiyun };
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
94*4882a593Smuzhiyun #define HAS_RMII 1
95*4882a593Smuzhiyun static const struct pinmux_config emac_pins[] = {
96*4882a593Smuzhiyun 	{ pinmux(14), 8, 2 },
97*4882a593Smuzhiyun 	{ pinmux(14), 8, 3 },
98*4882a593Smuzhiyun 	{ pinmux(14), 8, 4 },
99*4882a593Smuzhiyun 	{ pinmux(14), 8, 5 },
100*4882a593Smuzhiyun 	{ pinmux(14), 8, 6 },
101*4882a593Smuzhiyun 	{ pinmux(14), 8, 7 },
102*4882a593Smuzhiyun 	{ pinmux(15), 8, 1 },
103*4882a593Smuzhiyun 	{ pinmux(4), 8, 0 },
104*4882a593Smuzhiyun 	{ pinmux(4), 8, 1 }
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun #endif
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun #ifdef CONFIG_NAND_DAVINCI
109*4882a593Smuzhiyun const struct pinmux_config nand_pins[] = {
110*4882a593Smuzhiyun 	{ pinmux(7), 1, 0},	/* CS2 */
111*4882a593Smuzhiyun 	{ pinmux(7), 0, 1},	/* CS3  in three state*/
112*4882a593Smuzhiyun 	{ pinmux(7), 1, 4 },	/* EMA_WE */
113*4882a593Smuzhiyun 	{ pinmux(7), 1, 5 },	/* EMA_OE */
114*4882a593Smuzhiyun 	{ pinmux(9), 1, 0 },	/* EMA_D[7] */
115*4882a593Smuzhiyun 	{ pinmux(9), 1, 1 },	/* EMA_D[6] */
116*4882a593Smuzhiyun 	{ pinmux(9), 1, 2 },	/* EMA_D[5] */
117*4882a593Smuzhiyun 	{ pinmux(9), 1, 3 },	/* EMA_D[4] */
118*4882a593Smuzhiyun 	{ pinmux(9), 1, 4 },	/* EMA_D[3] */
119*4882a593Smuzhiyun 	{ pinmux(9), 1, 5 },	/* EMA_D[2] */
120*4882a593Smuzhiyun 	{ pinmux(9), 1, 6 },	/* EMA_D[1] */
121*4882a593Smuzhiyun 	{ pinmux(9), 1, 7 },	/* EMA_D[0] */
122*4882a593Smuzhiyun 	{ pinmux(12), 1, 5 },	/* EMA_A[2] */
123*4882a593Smuzhiyun 	{ pinmux(12), 1, 6 },	/* EMA_A[1] */
124*4882a593Smuzhiyun 	{ pinmux(6), 1, 0 }	/* EMA_CLK */
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun #endif
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun const struct pinmux_config gpio_pins[] = {
129*4882a593Smuzhiyun 	{ pinmux(13), 8, 0 }, /* GPIO6[15] RESETOUTn on SOM*/
130*4882a593Smuzhiyun 	{ pinmux(13), 8, 5 }, /* GPIO6[10] U0_SW0 on EA20-00101_2*/
131*4882a593Smuzhiyun 	{ pinmux(13), 8, 3 }, /* GPIO6[12] U0_SW1 on EA20-00101_2*/
132*4882a593Smuzhiyun 	{ pinmux(19), 8, 5 }, /* GPIO6[1]  DISP_ON */
133*4882a593Smuzhiyun 	{ pinmux(14), 8, 1 }  /* GPIO6[6]  LCD_B_PWR*/
134*4882a593Smuzhiyun };
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun const struct pinmux_config lcd_pins[] = {
137*4882a593Smuzhiyun 	{ pinmux(17), 2, 1 }, /* LCD_D_0 */
138*4882a593Smuzhiyun 	{ pinmux(17), 2, 0 }, /* LCD_D_1 */
139*4882a593Smuzhiyun 	{ pinmux(16), 2, 7 }, /* LCD_D_2 */
140*4882a593Smuzhiyun 	{ pinmux(16), 2, 6 }, /* LCD_D_3 */
141*4882a593Smuzhiyun 	{ pinmux(16), 2, 5 }, /* LCD_D_4 */
142*4882a593Smuzhiyun 	{ pinmux(16), 2, 4 }, /* LCD_D_5 */
143*4882a593Smuzhiyun 	{ pinmux(16), 2, 3 }, /* LCD_D_6 */
144*4882a593Smuzhiyun 	{ pinmux(16), 2, 2 }, /* LCD_D_7 */
145*4882a593Smuzhiyun 	{ pinmux(18), 2, 1 }, /* LCD_D_8 */
146*4882a593Smuzhiyun 	{ pinmux(18), 2, 0 }, /* LCD_D_9 */
147*4882a593Smuzhiyun 	{ pinmux(17), 2, 7 }, /* LCD_D_10 */
148*4882a593Smuzhiyun 	{ pinmux(17), 2, 6 }, /* LCD_D_11 */
149*4882a593Smuzhiyun 	{ pinmux(17), 2, 5 }, /* LCD_D_12 */
150*4882a593Smuzhiyun 	{ pinmux(17), 2, 4 }, /* LCD_D_13 */
151*4882a593Smuzhiyun 	{ pinmux(17), 2, 3 }, /* LCD_D_14 */
152*4882a593Smuzhiyun 	{ pinmux(17), 2, 2 }, /* LCD_D_15 */
153*4882a593Smuzhiyun 	{ pinmux(18), 2, 6 }, /* LCD_PCLK */
154*4882a593Smuzhiyun 	{ pinmux(19), 2, 0 }, /* LCD_HSYNC */
155*4882a593Smuzhiyun 	{ pinmux(19), 2, 1 }, /* LCD_VSYNC */
156*4882a593Smuzhiyun 	{ pinmux(19), 2, 6 }, /* DA850_NLCD_AC_ENB_CS */
157*4882a593Smuzhiyun };
158*4882a593Smuzhiyun 
159*4882a593Smuzhiyun const struct pinmux_config halten_pin[] = {
160*4882a593Smuzhiyun 	{ pinmux(3),  4, 2 } /* GPIO8[6] HALTEN */
161*4882a593Smuzhiyun };
162*4882a593Smuzhiyun 
163*4882a593Smuzhiyun static const struct pinmux_resource pinmuxes[] = {
164*4882a593Smuzhiyun #ifdef CONFIG_SPI_FLASH
165*4882a593Smuzhiyun 	PINMUX_ITEM(spi1_pins),
166*4882a593Smuzhiyun #endif
167*4882a593Smuzhiyun 	PINMUX_ITEM(uart_pins),
168*4882a593Smuzhiyun 	PINMUX_ITEM(i2c_pins),
169*4882a593Smuzhiyun #ifdef CONFIG_NAND_DAVINCI
170*4882a593Smuzhiyun 	PINMUX_ITEM(nand_pins),
171*4882a593Smuzhiyun #endif
172*4882a593Smuzhiyun #ifdef CONFIG_VIDEO
173*4882a593Smuzhiyun 	PINMUX_ITEM(lcd_pins),
174*4882a593Smuzhiyun #endif
175*4882a593Smuzhiyun };
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun static const struct lpsc_resource lpsc[] = {
178*4882a593Smuzhiyun 	{ DAVINCI_LPSC_AEMIF },	/* NAND, NOR */
179*4882a593Smuzhiyun 	{ DAVINCI_LPSC_SPI1 },	/* Serial Flash */
180*4882a593Smuzhiyun 	{ DAVINCI_LPSC_EMAC },	/* image download */
181*4882a593Smuzhiyun 	{ DAVINCI_LPSC_UART0 },	/* console */
182*4882a593Smuzhiyun 	{ DAVINCI_LPSC_GPIO },
183*4882a593Smuzhiyun 	{ DAVINCI_LPSC_LCDC }, /* LCD */
184*4882a593Smuzhiyun };
185*4882a593Smuzhiyun 
board_early_init_f(void)186*4882a593Smuzhiyun int board_early_init_f(void)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	/* PinMux for GPIO */
189*4882a593Smuzhiyun 	if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
190*4882a593Smuzhiyun 		return 1;
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun 	/* Set DISP_ON high to enable LCD output*/
193*4882a593Smuzhiyun 	gpio_direction_output(97, 1);
194*4882a593Smuzhiyun 
195*4882a593Smuzhiyun 	/* Set the RESETOUTn low */
196*4882a593Smuzhiyun 	gpio_direction_output(111, 0);
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun 	/* Set U0_SW0 low for UART0 as console*/
199*4882a593Smuzhiyun 	gpio_direction_output(106, 0);
200*4882a593Smuzhiyun 
201*4882a593Smuzhiyun 	/* Set U0_SW1 low for UART0 as console*/
202*4882a593Smuzhiyun 	gpio_direction_output(108, 0);
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun 	/* Set LCD_B_PWR low to power down LCD Backlight*/
205*4882a593Smuzhiyun 	gpio_direction_output(102, 0);
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	irq_init();
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	/*
210*4882a593Smuzhiyun 	 * NAND CS setup - cycle counts based on da850evm NAND timings in the
211*4882a593Smuzhiyun 	 * Linux kernel @ 25MHz EMIFA
212*4882a593Smuzhiyun 	 */
213*4882a593Smuzhiyun #ifdef CONFIG_NAND_DAVINCI
214*4882a593Smuzhiyun 	writel((DAVINCI_ABCR_WSETUP(0) |
215*4882a593Smuzhiyun 		DAVINCI_ABCR_WSTROBE(1) |
216*4882a593Smuzhiyun 		DAVINCI_ABCR_WHOLD(0) |
217*4882a593Smuzhiyun 		DAVINCI_ABCR_RSETUP(0) |
218*4882a593Smuzhiyun 		DAVINCI_ABCR_RSTROBE(1) |
219*4882a593Smuzhiyun 		DAVINCI_ABCR_RHOLD(0) |
220*4882a593Smuzhiyun 		DAVINCI_ABCR_TA(0) |
221*4882a593Smuzhiyun 		DAVINCI_ABCR_ASIZE_8BIT),
222*4882a593Smuzhiyun 	       &davinci_emif_regs->ab1cr); /* CS2 */
223*4882a593Smuzhiyun #endif
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun 	/*
226*4882a593Smuzhiyun 	 * Power on required peripherals
227*4882a593Smuzhiyun 	 * ARM does not have access by default to PSC0 and PSC1
228*4882a593Smuzhiyun 	 * assuming here that the DSP bootloader has set the IOPU
229*4882a593Smuzhiyun 	 * such that PSC access is available to ARM
230*4882a593Smuzhiyun 	 */
231*4882a593Smuzhiyun 	if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
232*4882a593Smuzhiyun 		return 1;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	/* setup the SUSPSRC for ARM to control emulation suspend */
235*4882a593Smuzhiyun 	writel(readl(&davinci_syscfg_regs->suspsrc) &
236*4882a593Smuzhiyun 	       ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
237*4882a593Smuzhiyun 		 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
238*4882a593Smuzhiyun 		 DAVINCI_SYSCFG_SUSPSRC_UART0),
239*4882a593Smuzhiyun 	       &davinci_syscfg_regs->suspsrc);
240*4882a593Smuzhiyun 
241*4882a593Smuzhiyun 	/* configure pinmux settings */
242*4882a593Smuzhiyun 	if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
243*4882a593Smuzhiyun 		return 1;
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
246*4882a593Smuzhiyun 	if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
247*4882a593Smuzhiyun 		return 1;
248*4882a593Smuzhiyun 
249*4882a593Smuzhiyun 	davinci_emac_mii_mode_sel(HAS_RMII);
250*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_TI_EMAC */
251*4882a593Smuzhiyun 
252*4882a593Smuzhiyun 	/* enable the console UART */
253*4882a593Smuzhiyun 	writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
254*4882a593Smuzhiyun 		DAVINCI_UART_PWREMU_MGMT_UTRST),
255*4882a593Smuzhiyun 	       &davinci_uart0_ctrl_regs->pwremu_mgmt);
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	/*
258*4882a593Smuzhiyun 	 * Reconfigure the LCDC priority to the highest to ensure that
259*4882a593Smuzhiyun 	 * the throughput/latency requirements for the LCDC are met.
260*4882a593Smuzhiyun 	 */
261*4882a593Smuzhiyun 	writel(readl(&davinci_syscfg_regs->mstpri[2]) & 0x0fffffff,
262*4882a593Smuzhiyun 	       &davinci_syscfg_regs->mstpri[2]);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	return 0;
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun /*
269*4882a593Smuzhiyun  * Do not overwrite the console
270*4882a593Smuzhiyun  * Use always serial for U-Boot console
271*4882a593Smuzhiyun  */
overwrite_console(void)272*4882a593Smuzhiyun int overwrite_console(void)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	return 1;
275*4882a593Smuzhiyun }
276*4882a593Smuzhiyun 
board_init(void)277*4882a593Smuzhiyun int board_init(void)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun 	/* arch number of the board */
280*4882a593Smuzhiyun 	gd->bd->bi_arch_number = MACH_TYPE_EA20;
281*4882a593Smuzhiyun 
282*4882a593Smuzhiyun 	/* address of boot parameters */
283*4882a593Smuzhiyun 	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 	da8xx_video_init(&lcd_panel, &lcd_cfg, 16);
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun 	return 0;
288*4882a593Smuzhiyun }
289*4882a593Smuzhiyun 
290*4882a593Smuzhiyun #ifdef CONFIG_BOARD_LATE_INIT
291*4882a593Smuzhiyun 
board_late_init(void)292*4882a593Smuzhiyun int board_late_init(void)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun 	unsigned char buf[2];
295*4882a593Smuzhiyun 	int ret;
296*4882a593Smuzhiyun 
297*4882a593Smuzhiyun 	/* PinMux for HALTEN */
298*4882a593Smuzhiyun 	if (davinci_configure_pin_mux(halten_pin, ARRAY_SIZE(halten_pin)) != 0)
299*4882a593Smuzhiyun 		return 1;
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun 	/* Set HALTEN to high */
302*4882a593Smuzhiyun 	gpio_direction_output(134, 1);
303*4882a593Smuzhiyun 
304*4882a593Smuzhiyun 	/* Set fixed contrast settings for LCD via I2C potentiometer */
305*4882a593Smuzhiyun 	buf[0] = 0x00;
306*4882a593Smuzhiyun 	buf[1] = 0xd7;
307*4882a593Smuzhiyun 	ret = i2c_write(0x2e, 6, 1, buf, 2);
308*4882a593Smuzhiyun 	if (ret)
309*4882a593Smuzhiyun 		puts("\nContrast Settings FAILED\n");
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun 	/* Set LCD_B_PWR high to power up LCD Backlight*/
312*4882a593Smuzhiyun 	gpio_set_value(102, 1);
313*4882a593Smuzhiyun 	return 0;
314*4882a593Smuzhiyun }
315*4882a593Smuzhiyun #endif /* CONFIG_BOARD_LATE_INIT */
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun #ifdef CONFIG_DRIVER_TI_EMAC
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun /*
320*4882a593Smuzhiyun  * Initializes on-board ethernet controllers.
321*4882a593Smuzhiyun  */
board_eth_init(bd_t * bis)322*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
323*4882a593Smuzhiyun {
324*4882a593Smuzhiyun 	if (!davinci_emac_initialize()) {
325*4882a593Smuzhiyun 		printf("Error: Ethernet init failed!\n");
326*4882a593Smuzhiyun 		return -1;
327*4882a593Smuzhiyun 	}
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun 	/*
330*4882a593Smuzhiyun 	 * This board has a RMII PHY. However, the MDC line on the SOM
331*4882a593Smuzhiyun 	 * must not be disabled (there is no MII PHY on the
332*4882a593Smuzhiyun 	 * baseboard) via the GPIO2[6], because this pin
333*4882a593Smuzhiyun 	 * disables at the same time the SPI flash.
334*4882a593Smuzhiyun 	 */
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	return 0;
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun #endif /* CONFIG_DRIVER_TI_EMAC */
339