1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2010-2017 CS Systemes d'Information
3*4882a593Smuzhiyun * Florent Trinh Thai <florent.trinh-thai@c-s.fr>
4*4882a593Smuzhiyun * Christophe Leroy <christophe.leroy@c-s.fr>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <config.h>
10*4882a593Smuzhiyun #include <common.h>
11*4882a593Smuzhiyun #include <nand.h>
12*4882a593Smuzhiyun #include <asm/io.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #define BIT_CLE ((unsigned short)0x0800)
15*4882a593Smuzhiyun #define BIT_ALE ((unsigned short)0x0400)
16*4882a593Smuzhiyun #define BIT_NCE ((unsigned short)0x1000)
17*4882a593Smuzhiyun
nand_hwcontrol(struct mtd_info * mtdinfo,int cmd,unsigned int ctrl)18*4882a593Smuzhiyun static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun struct nand_chip *this = mtdinfo->priv;
21*4882a593Smuzhiyun immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
22*4882a593Smuzhiyun unsigned short pddat = 0;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* The hardware control change */
25*4882a593Smuzhiyun if (ctrl & NAND_CTRL_CHANGE) {
26*4882a593Smuzhiyun pddat = in_be16(&immr->im_ioport.iop_pddat);
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* Clearing ALE and CLE */
29*4882a593Smuzhiyun pddat &= ~(BIT_CLE | BIT_ALE);
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Driving NCE pin */
32*4882a593Smuzhiyun if (ctrl & NAND_NCE)
33*4882a593Smuzhiyun pddat &= ~BIT_NCE;
34*4882a593Smuzhiyun else
35*4882a593Smuzhiyun pddat |= BIT_NCE;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* Driving CLE and ALE pin */
38*4882a593Smuzhiyun if (ctrl & NAND_CLE)
39*4882a593Smuzhiyun pddat |= BIT_CLE;
40*4882a593Smuzhiyun if (ctrl & NAND_ALE)
41*4882a593Smuzhiyun pddat |= BIT_ALE;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun out_be16(&immr->im_ioport.iop_pddat, pddat);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun /* Writing the command */
47*4882a593Smuzhiyun if (cmd != NAND_CMD_NONE)
48*4882a593Smuzhiyun out_8(this->IO_ADDR_W, cmd);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
board_nand_init(struct nand_chip * nand)51*4882a593Smuzhiyun int board_nand_init(struct nand_chip *nand)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun immap_t __iomem *immr = (immap_t __iomem *)CONFIG_SYS_IMMR;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Set GPIO Port */
56*4882a593Smuzhiyun setbits_be16(&immr->im_ioport.iop_pddir, 0x1c00);
57*4882a593Smuzhiyun clrbits_be16(&immr->im_ioport.iop_pdpar, 0x1c00);
58*4882a593Smuzhiyun clrsetbits_be16(&immr->im_ioport.iop_pddat, 0x0c00, 0x1000);
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun nand->chip_delay = 60;
61*4882a593Smuzhiyun nand->ecc.mode = NAND_ECC_SOFT;
62*4882a593Smuzhiyun nand->cmd_ctrl = nand_hwcontrol;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
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