xref: /OK3568_Linux_fs/u-boot/board/congatec/conga-qeval20-qa3-e3845/conga-qeval20-qa3.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright (C) 2016 Stefan Roese <sr@denx.de>
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * SPDX-License-Identifier:	GPL-2.0+
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <i2c.h>
9*4882a593Smuzhiyun #include <winbond_w83627.h>
10*4882a593Smuzhiyun #include <asm/gpio.h>
11*4882a593Smuzhiyun #include <asm/ibmpc.h>
12*4882a593Smuzhiyun #include <asm/pnp_def.h>
13*4882a593Smuzhiyun 
board_early_init_f(void)14*4882a593Smuzhiyun int board_early_init_f(void)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun #ifndef CONFIG_INTERNAL_UART
17*4882a593Smuzhiyun 	/*
18*4882a593Smuzhiyun 	 * The FSP enables the BayTrail internal legacy UART (again).
19*4882a593Smuzhiyun 	 * Disable it again, so that the Winbond one can be used.
20*4882a593Smuzhiyun 	 */
21*4882a593Smuzhiyun 	setup_internal_uart(0);
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun 	/* Enable the legacy UART in the Winbond W83627 Super IO chip */
24*4882a593Smuzhiyun 	winbond_enable_serial(PNP_DEV(WINBOND_IO_PORT, W83627DHG_SP1),
25*4882a593Smuzhiyun 			      UART0_BASE, UART0_IRQ);
26*4882a593Smuzhiyun #endif
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun 	return 0;
29*4882a593Smuzhiyun }
30*4882a593Smuzhiyun 
board_late_init(void)31*4882a593Smuzhiyun int board_late_init(void)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun 	struct udevice *dev;
34*4882a593Smuzhiyun 	u8 buf[8];
35*4882a593Smuzhiyun 	int ret;
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun 	/* Configure SMSC USB2513 USB Hub: 7bit address 0x2c */
38*4882a593Smuzhiyun 	ret = i2c_get_chip_for_busnum(0, 0x2c, 1, &dev);
39*4882a593Smuzhiyun 	if (ret) {
40*4882a593Smuzhiyun 		printf("Cannot find USB2513: %d\n", ret);
41*4882a593Smuzhiyun 		return 0;
42*4882a593Smuzhiyun 	}
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun 	/*
45*4882a593Smuzhiyun 	 * The first access to the USB Hub fails sometimes, so lets read
46*4882a593Smuzhiyun 	 * a dummy byte to be sure here
47*4882a593Smuzhiyun 	 */
48*4882a593Smuzhiyun 	dm_i2c_read(dev, 0x00, buf, 1);
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun 	/*
51*4882a593Smuzhiyun 	 * The SMSC hub is not visible on the I2C bus after the first
52*4882a593Smuzhiyun 	 * configuration at power-up. The following code deliberately
53*4882a593Smuzhiyun 	 * does not report upon failure of these I2C write calls.
54*4882a593Smuzhiyun 	 */
55*4882a593Smuzhiyun 	buf[0] = 0x93;
56*4882a593Smuzhiyun 	dm_i2c_write(dev, 0x06, buf, 1);
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	buf[0] = 0xaa;
59*4882a593Smuzhiyun 	dm_i2c_write(dev, 0xf8, buf, 1);
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun 	buf[0] = 0x0f;
62*4882a593Smuzhiyun 	dm_i2c_write(dev, 0xfa, buf, 1);
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun 	buf[0] = 0x01;
65*4882a593Smuzhiyun 	dm_i2c_write(dev, 0xff, buf, 1);
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun 	return 0;
68*4882a593Smuzhiyun }
69