1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010-2012 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <common.h> 9*4882a593Smuzhiyun #include <asm/io.h> 10*4882a593Smuzhiyun #include <asm/arch/tegra.h> 11*4882a593Smuzhiyun #include <asm/arch/clock.h> 12*4882a593Smuzhiyun #include <asm/arch/funcmux.h> 13*4882a593Smuzhiyun #include <asm/arch/pinmux.h> 14*4882a593Smuzhiyun #include <asm/gpio.h> 15*4882a593Smuzhiyun #include <i2c.h> 16*4882a593Smuzhiyun pin_mux_usb(void)17*4882a593Smuzhiyunvoid pin_mux_usb(void) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO 21*4882a593Smuzhiyun * in the current device tree. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_UAC); 24*4882a593Smuzhiyun } 25*4882a593Smuzhiyun pin_mux_spi(void)26*4882a593Smuzhiyunvoid pin_mux_spi(void) 27*4882a593Smuzhiyun { 28*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SPI1, FUNCMUX_SPI1_GMC_GMD); 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun /* 32*4882a593Smuzhiyun * Routine: pin_mux_mmc 33*4882a593Smuzhiyun * Description: setup the pin muxes/tristate values for the SDMMC(s) 34*4882a593Smuzhiyun */ pin_mux_mmc(void)35*4882a593Smuzhiyunvoid pin_mux_mmc(void) 36*4882a593Smuzhiyun { 37*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SDMMC1, FUNCMUX_SDMMC1_SDIO1_4BIT); 38*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* For CD GPIO PP1 */ 41*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_DAP3); 42*4882a593Smuzhiyun } 43