1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (c) 2004-2008 Texas Instruments 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * (C) Copyright 2002 5*4882a593Smuzhiyun * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunOUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 11*4882a593SmuzhiyunOUTPUT_ARCH(arm) 12*4882a593SmuzhiyunENTRY(_start) 13*4882a593SmuzhiyunSECTIONS 14*4882a593Smuzhiyun{ 15*4882a593Smuzhiyun . = 0x00000000; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun . = ALIGN(4); 18*4882a593Smuzhiyun .text : 19*4882a593Smuzhiyun { 20*4882a593Smuzhiyun *(.__image_copy_start) 21*4882a593Smuzhiyun *(.vectors) 22*4882a593Smuzhiyun CPUDIR/start.o (.text*) 23*4882a593Smuzhiyun board/compulab/cm_t335/built-in.o (.text*) 24*4882a593Smuzhiyun *(.text*) 25*4882a593Smuzhiyun } 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun . = ALIGN(4); 28*4882a593Smuzhiyun .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun . = ALIGN(4); 31*4882a593Smuzhiyun .data : { 32*4882a593Smuzhiyun *(.data*) 33*4882a593Smuzhiyun } 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun . = ALIGN(4); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun . = .; 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun . = ALIGN(4); 40*4882a593Smuzhiyun .u_boot_list : { 41*4882a593Smuzhiyun KEEP(*(SORT(.u_boot_list*))); 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun . = ALIGN(4); 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun .image_copy_end : 47*4882a593Smuzhiyun { 48*4882a593Smuzhiyun *(.__image_copy_end) 49*4882a593Smuzhiyun } 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun .rel_dyn_start : 52*4882a593Smuzhiyun { 53*4882a593Smuzhiyun *(.__rel_dyn_start) 54*4882a593Smuzhiyun } 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun .rel.dyn : { 57*4882a593Smuzhiyun *(.rel*) 58*4882a593Smuzhiyun } 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun .rel_dyn_end : 61*4882a593Smuzhiyun { 62*4882a593Smuzhiyun *(.__rel_dyn_end) 63*4882a593Smuzhiyun } 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun .hash : { *(.hash*) } 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun .end : 68*4882a593Smuzhiyun { 69*4882a593Smuzhiyun *(.__end) 70*4882a593Smuzhiyun } 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun _image_binary_end = .; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * Deprecated: this MMU section is used by pxa at present but 76*4882a593Smuzhiyun * should not be used by new boards/CPUs. 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun . = ALIGN(4096); 79*4882a593Smuzhiyun .mmutable : { 80*4882a593Smuzhiyun *(.mmutable) 81*4882a593Smuzhiyun } 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun/* 84*4882a593Smuzhiyun * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c 85*4882a593Smuzhiyun * __bss_base and __bss_limit are for linker only (overlay ordering) 86*4882a593Smuzhiyun */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun .bss_start __rel_dyn_start (OVERLAY) : { 89*4882a593Smuzhiyun KEEP(*(.__bss_start)); 90*4882a593Smuzhiyun __bss_base = .; 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun .bss __bss_base (OVERLAY) : { 94*4882a593Smuzhiyun *(.bss*) 95*4882a593Smuzhiyun . = ALIGN(4); 96*4882a593Smuzhiyun __bss_limit = .; 97*4882a593Smuzhiyun } 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun .bss_end __bss_limit (OVERLAY) : { 100*4882a593Smuzhiyun KEEP(*(.__bss_end)); 101*4882a593Smuzhiyun } 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun .dynsym _image_binary_end : { *(.dynsym) } 104*4882a593Smuzhiyun .dynbss : { *(.dynbss) } 105*4882a593Smuzhiyun .dynstr : { *(.dynstr*) } 106*4882a593Smuzhiyun .dynamic : { *(.dynamic*) } 107*4882a593Smuzhiyun .plt : { *(.plt*) } 108*4882a593Smuzhiyun .interp : { *(.interp*) } 109*4882a593Smuzhiyun .gnu : { *(.gnu*) } 110*4882a593Smuzhiyun .ARM.exidx : { *(.ARM.exidx*) } 111*4882a593Smuzhiyun} 112