1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SPL specific code for Compulab CM-T335 board
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Board functions for Compulab CM-T335 board
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Ilya Ledvich <ilya@compulab.co.il>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <errno.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include <asm/arch/ddr_defs.h>
17*4882a593Smuzhiyun #include <asm/arch/clock.h>
18*4882a593Smuzhiyun #include <asm/arch/clocks_am33xx.h>
19*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
20*4882a593Smuzhiyun #include <asm/arch/hardware_am33xx.h>
21*4882a593Smuzhiyun #include <linux/sizes.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun const struct ctrl_ioregs ioregs = {
24*4882a593Smuzhiyun .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
25*4882a593Smuzhiyun .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
26*4882a593Smuzhiyun .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
27*4882a593Smuzhiyun .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
28*4882a593Smuzhiyun .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static const struct ddr_data ddr3_data = {
32*4882a593Smuzhiyun .datardsratio0 = MT41J128MJT125_RD_DQS,
33*4882a593Smuzhiyun .datawdsratio0 = MT41J128MJT125_WR_DQS,
34*4882a593Smuzhiyun .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
35*4882a593Smuzhiyun .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun static const struct cmd_control ddr3_cmd_ctrl_data = {
39*4882a593Smuzhiyun .cmd0csratio = MT41J128MJT125_RATIO,
40*4882a593Smuzhiyun .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun .cmd1csratio = MT41J128MJT125_RATIO,
43*4882a593Smuzhiyun .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun .cmd2csratio = MT41J128MJT125_RATIO,
46*4882a593Smuzhiyun .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static struct emif_regs ddr3_emif_reg_data = {
50*4882a593Smuzhiyun .sdram_config = MT41J128MJT125_EMIF_SDCFG,
51*4882a593Smuzhiyun .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
52*4882a593Smuzhiyun .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
53*4882a593Smuzhiyun .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
54*4882a593Smuzhiyun .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
55*4882a593Smuzhiyun .zq_config = MT41J128MJT125_ZQ_CFG,
56*4882a593Smuzhiyun .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
57*4882a593Smuzhiyun PHY_EN_DYN_PWRDN,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun const struct dpll_params dpll_ddr = {
61*4882a593Smuzhiyun /* M N M2 M3 M4 M5 M6 */
62*4882a593Smuzhiyun 303, (V_OSCK/1000000) - 1, 1, -1, -1, -1, -1};
63*4882a593Smuzhiyun
am33xx_spl_board_init(void)64*4882a593Smuzhiyun void am33xx_spl_board_init(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* Get the frequency */
69*4882a593Smuzhiyun dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun /* Set CORE Frequencies to OPP100 */
72*4882a593Smuzhiyun do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun /* Set MPU Frequency to what we detected now that voltages are set */
75*4882a593Smuzhiyun do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
get_dpll_ddr_params(void)78*4882a593Smuzhiyun const struct dpll_params *get_dpll_ddr_params(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun return &dpll_ddr;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
probe_sdram_size(long size)83*4882a593Smuzhiyun static void probe_sdram_size(long size)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun switch (size) {
86*4882a593Smuzhiyun case SZ_512M:
87*4882a593Smuzhiyun ddr3_emif_reg_data.sdram_config = MT41J256MJT125_EMIF_SDCFG;
88*4882a593Smuzhiyun break;
89*4882a593Smuzhiyun case SZ_256M:
90*4882a593Smuzhiyun ddr3_emif_reg_data.sdram_config = MT41J128MJT125_EMIF_SDCFG;
91*4882a593Smuzhiyun break;
92*4882a593Smuzhiyun case SZ_128M:
93*4882a593Smuzhiyun ddr3_emif_reg_data.sdram_config = MT41J64MJT125_EMIF_SDCFG;
94*4882a593Smuzhiyun break;
95*4882a593Smuzhiyun default:
96*4882a593Smuzhiyun puts("Failed configuring DRAM, resetting...\n\n");
97*4882a593Smuzhiyun reset_cpu(0);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
100*4882a593Smuzhiyun config_ddr(303, &ioregs, &ddr3_data,
101*4882a593Smuzhiyun &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
sdram_init(void)104*4882a593Smuzhiyun void sdram_init(void)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun long size = SZ_1G;
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun do {
109*4882a593Smuzhiyun size = size / 2;
110*4882a593Smuzhiyun probe_sdram_size(size);
111*4882a593Smuzhiyun } while (get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, size) < size);
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun return;
114*4882a593Smuzhiyun }
115