1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Code used by both U-Boot and SPL for Compulab CM-FX6
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * Author: Nikita Kiryanov <nikita@compulab.co.il>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
13*4882a593Smuzhiyun #include <asm/gpio.h>
14*4882a593Smuzhiyun #include <asm/mach-imx/spi.h>
15*4882a593Smuzhiyun #include <fsl_esdhc.h>
16*4882a593Smuzhiyun #include "common.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #ifdef CONFIG_FSL_ESDHC
21*4882a593Smuzhiyun #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
22*4882a593Smuzhiyun PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
23*4882a593Smuzhiyun PAD_CTL_SRE_FAST | PAD_CTL_HYS)
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun static iomux_v3_cfg_t const usdhc_pads[] = {
26*4882a593Smuzhiyun IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
27*4882a593Smuzhiyun IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
28*4882a593Smuzhiyun IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
29*4882a593Smuzhiyun IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
30*4882a593Smuzhiyun IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
31*4882a593Smuzhiyun IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
34*4882a593Smuzhiyun IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
35*4882a593Smuzhiyun IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
36*4882a593Smuzhiyun IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
37*4882a593Smuzhiyun IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
38*4882a593Smuzhiyun IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
41*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
42*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
43*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
44*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
45*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
46*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
47*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
48*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
49*4882a593Smuzhiyun IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
50*4882a593Smuzhiyun };
51*4882a593Smuzhiyun
cm_fx6_set_usdhc_iomux(void)52*4882a593Smuzhiyun void cm_fx6_set_usdhc_iomux(void)
53*4882a593Smuzhiyun {
54*4882a593Smuzhiyun SETUP_IOMUX_PADS(usdhc_pads);
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /* CINS bit doesn't work, so always try to access the MMC card */
board_mmc_getcd(struct mmc * mmc)58*4882a593Smuzhiyun int board_mmc_getcd(struct mmc *mmc)
59*4882a593Smuzhiyun {
60*4882a593Smuzhiyun return 1;
61*4882a593Smuzhiyun }
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun #ifdef CONFIG_MXC_SPI
65*4882a593Smuzhiyun #define ECSPI_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_SPEED_MED | \
66*4882a593Smuzhiyun PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun static iomux_v3_cfg_t const ecspi_pads[] = {
69*4882a593Smuzhiyun IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
70*4882a593Smuzhiyun IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
71*4882a593Smuzhiyun IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
72*4882a593Smuzhiyun IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
73*4882a593Smuzhiyun IOMUX_PADS(PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(ECSPI_PAD_CTRL)),
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
cm_fx6_set_ecspi_iomux(void)76*4882a593Smuzhiyun void cm_fx6_set_ecspi_iomux(void)
77*4882a593Smuzhiyun {
78*4882a593Smuzhiyun SETUP_IOMUX_PADS(ecspi_pads);
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
board_spi_cs_gpio(unsigned bus,unsigned cs)81*4882a593Smuzhiyun int board_spi_cs_gpio(unsigned bus, unsigned cs)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun return (bus == 0 && cs == 0) ? (CM_FX6_ECSPI_BUS0_CS0) : -1;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun #endif
86