1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2000-2003
3*4882a593Smuzhiyun * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <console.h>
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
12*4882a593Smuzhiyun #define FLASH_BANK_SIZE 0x200000
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
15*4882a593Smuzhiyun
flash_print_info(flash_info_t * info)16*4882a593Smuzhiyun void flash_print_info (flash_info_t * info)
17*4882a593Smuzhiyun {
18*4882a593Smuzhiyun int i;
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun switch (info->flash_id & FLASH_VENDMASK) {
21*4882a593Smuzhiyun case (AMD_MANUFACT & FLASH_VENDMASK):
22*4882a593Smuzhiyun printf ("AMD: ");
23*4882a593Smuzhiyun break;
24*4882a593Smuzhiyun default:
25*4882a593Smuzhiyun printf ("Unknown Vendor ");
26*4882a593Smuzhiyun break;
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun switch (info->flash_id & FLASH_TYPEMASK) {
30*4882a593Smuzhiyun case (AMD_ID_PL160CB & FLASH_TYPEMASK):
31*4882a593Smuzhiyun printf ("AM29PL160CB (16Mbit)\n");
32*4882a593Smuzhiyun break;
33*4882a593Smuzhiyun default:
34*4882a593Smuzhiyun printf ("Unknown Chip Type\n");
35*4882a593Smuzhiyun goto Done;
36*4882a593Smuzhiyun break;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun printf (" Size: %ld MB in %d Sectors\n",
40*4882a593Smuzhiyun info->size >> 20, info->sector_count);
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun printf (" Sector Start Addresses:");
43*4882a593Smuzhiyun for (i = 0; i < info->sector_count; i++) {
44*4882a593Smuzhiyun if ((i % 5) == 0) {
45*4882a593Smuzhiyun printf ("\n ");
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun printf (" %08lX%s", info->start[i],
48*4882a593Smuzhiyun info->protect[i] ? " (RO)" : " ");
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun printf ("\n");
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun Done:
53*4882a593Smuzhiyun return;
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun
flash_init(void)57*4882a593Smuzhiyun unsigned long flash_init (void)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun int i, j;
60*4882a593Smuzhiyun ulong size = 0;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
63*4882a593Smuzhiyun ulong flashbase = 0;
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun flash_info[i].flash_id =
66*4882a593Smuzhiyun (AMD_MANUFACT & FLASH_VENDMASK) |
67*4882a593Smuzhiyun (AMD_ID_PL160CB & FLASH_TYPEMASK);
68*4882a593Smuzhiyun flash_info[i].size = FLASH_BANK_SIZE;
69*4882a593Smuzhiyun flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
70*4882a593Smuzhiyun memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
71*4882a593Smuzhiyun if (i == 0)
72*4882a593Smuzhiyun flashbase = PHYS_FLASH_1;
73*4882a593Smuzhiyun else
74*4882a593Smuzhiyun panic ("configured to many flash banks!\n");
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun for (j = 0; j < flash_info[i].sector_count; j++) {
77*4882a593Smuzhiyun if (j == 0) {
78*4882a593Smuzhiyun /* 1st is 16 KiB */
79*4882a593Smuzhiyun flash_info[i].start[j] = flashbase;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun if ((j >= 1) && (j <= 2)) {
82*4882a593Smuzhiyun /* 2nd and 3rd are 8 KiB */
83*4882a593Smuzhiyun flash_info[i].start[j] =
84*4882a593Smuzhiyun flashbase + 0x4000 + 0x2000 * (j - 1);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun if (j == 3) {
87*4882a593Smuzhiyun /* 4th is 224 KiB */
88*4882a593Smuzhiyun flash_info[i].start[j] = flashbase + 0x8000;
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun if ((j >= 4) && (j <= 10)) {
91*4882a593Smuzhiyun /* rest is 256 KiB */
92*4882a593Smuzhiyun flash_info[i].start[j] =
93*4882a593Smuzhiyun flashbase + 0x40000 + 0x40000 * (j -
94*4882a593Smuzhiyun 4);
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun size += flash_info[i].size;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun flash_protect (FLAG_PROTECT_SET,
101*4882a593Smuzhiyun CONFIG_SYS_FLASH_BASE,
102*4882a593Smuzhiyun CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return size;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun #define CMD_READ_ARRAY 0x00F0
109*4882a593Smuzhiyun #define CMD_UNLOCK1 0x00AA
110*4882a593Smuzhiyun #define CMD_UNLOCK2 0x0055
111*4882a593Smuzhiyun #define CMD_ERASE_SETUP 0x0080
112*4882a593Smuzhiyun #define CMD_ERASE_CONFIRM 0x0030
113*4882a593Smuzhiyun #define CMD_PROGRAM 0x00A0
114*4882a593Smuzhiyun #define CMD_UNLOCK_BYPASS 0x0020
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun #define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
117*4882a593Smuzhiyun #define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun #define BIT_ERASE_DONE 0x0080
120*4882a593Smuzhiyun #define BIT_RDY_MASK 0x0080
121*4882a593Smuzhiyun #define BIT_PROGRAM_ERROR 0x0020
122*4882a593Smuzhiyun #define BIT_TIMEOUT 0x80000000 /* our flag */
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #define READY 1
125*4882a593Smuzhiyun #define ERR 2
126*4882a593Smuzhiyun #define TMO 4
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun
flash_erase(flash_info_t * info,int s_first,int s_last)129*4882a593Smuzhiyun int flash_erase (flash_info_t * info, int s_first, int s_last)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun ulong result;
132*4882a593Smuzhiyun int iflag, cflag, prot, sect;
133*4882a593Smuzhiyun int rc = ERR_OK;
134*4882a593Smuzhiyun int chip1;
135*4882a593Smuzhiyun ulong start;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /* first look for protection bits */
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun if (info->flash_id == FLASH_UNKNOWN)
140*4882a593Smuzhiyun return ERR_UNKNOWN_FLASH_TYPE;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun if ((s_first < 0) || (s_first > s_last)) {
143*4882a593Smuzhiyun return ERR_INVAL;
144*4882a593Smuzhiyun }
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if ((info->flash_id & FLASH_VENDMASK) !=
147*4882a593Smuzhiyun (AMD_MANUFACT & FLASH_VENDMASK)) {
148*4882a593Smuzhiyun return ERR_UNKNOWN_FLASH_VENDOR;
149*4882a593Smuzhiyun }
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun prot = 0;
152*4882a593Smuzhiyun for (sect = s_first; sect <= s_last; ++sect) {
153*4882a593Smuzhiyun if (info->protect[sect]) {
154*4882a593Smuzhiyun prot++;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun if (prot)
158*4882a593Smuzhiyun return ERR_PROTECTED;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /*
161*4882a593Smuzhiyun * Disable interrupts which might cause a timeout
162*4882a593Smuzhiyun * here. Remember that our exception vectors are
163*4882a593Smuzhiyun * at address 0 in the flash, and we don't want a
164*4882a593Smuzhiyun * (ticker) exception to happen while the flash
165*4882a593Smuzhiyun * chip is in programming mode.
166*4882a593Smuzhiyun */
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun cflag = icache_status ();
169*4882a593Smuzhiyun icache_disable ();
170*4882a593Smuzhiyun iflag = disable_interrupts ();
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun printf ("\n");
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun /* Start erase on unprotected sectors */
175*4882a593Smuzhiyun for (sect = s_first; sect <= s_last && !ctrlc (); sect++) {
176*4882a593Smuzhiyun printf ("Erasing sector %2d ... ", sect);
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun /* arm simple, non interrupt dependent timer */
179*4882a593Smuzhiyun start = get_timer(0);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun if (info->protect[sect] == 0) { /* not protected */
182*4882a593Smuzhiyun volatile u16 *addr =
183*4882a593Smuzhiyun (volatile u16 *) (info->start[sect]);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun MEM_FLASH_ADDR1 = CMD_UNLOCK1;
186*4882a593Smuzhiyun MEM_FLASH_ADDR2 = CMD_UNLOCK2;
187*4882a593Smuzhiyun MEM_FLASH_ADDR1 = CMD_ERASE_SETUP;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun MEM_FLASH_ADDR1 = CMD_UNLOCK1;
190*4882a593Smuzhiyun MEM_FLASH_ADDR2 = CMD_UNLOCK2;
191*4882a593Smuzhiyun *addr = CMD_ERASE_CONFIRM;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun /* wait until flash is ready */
194*4882a593Smuzhiyun chip1 = 0;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun do {
197*4882a593Smuzhiyun result = *addr;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun /* check timeout */
200*4882a593Smuzhiyun if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
201*4882a593Smuzhiyun MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
202*4882a593Smuzhiyun chip1 = TMO;
203*4882a593Smuzhiyun break;
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun if (!chip1
207*4882a593Smuzhiyun && (result & 0xFFFF) & BIT_ERASE_DONE)
208*4882a593Smuzhiyun chip1 = READY;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun } while (!chip1);
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun if (chip1 == ERR) {
215*4882a593Smuzhiyun rc = ERR_PROG_ERROR;
216*4882a593Smuzhiyun goto outahere;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun if (chip1 == TMO) {
219*4882a593Smuzhiyun rc = ERR_TIMEOUT;
220*4882a593Smuzhiyun goto outahere;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun printf ("ok.\n");
224*4882a593Smuzhiyun } else { /* it was protected */
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun printf ("protected!\n");
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun if (ctrlc ())
231*4882a593Smuzhiyun printf ("User Interrupt!\n");
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun outahere:
234*4882a593Smuzhiyun /* allow flash to settle - wait 10 ms */
235*4882a593Smuzhiyun udelay (10000);
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun if (iflag)
238*4882a593Smuzhiyun enable_interrupts ();
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun if (cflag)
241*4882a593Smuzhiyun icache_enable ();
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun return rc;
244*4882a593Smuzhiyun }
245*4882a593Smuzhiyun
write_word(flash_info_t * info,ulong dest,ulong data)246*4882a593Smuzhiyun static int write_word (flash_info_t * info, ulong dest, ulong data)
247*4882a593Smuzhiyun {
248*4882a593Smuzhiyun volatile u16 *addr = (volatile u16 *) dest;
249*4882a593Smuzhiyun ulong result;
250*4882a593Smuzhiyun int rc = ERR_OK;
251*4882a593Smuzhiyun int cflag, iflag;
252*4882a593Smuzhiyun int chip1;
253*4882a593Smuzhiyun ulong start;
254*4882a593Smuzhiyun
255*4882a593Smuzhiyun /*
256*4882a593Smuzhiyun * Check if Flash is (sufficiently) erased
257*4882a593Smuzhiyun */
258*4882a593Smuzhiyun result = *addr;
259*4882a593Smuzhiyun if ((result & data) != data)
260*4882a593Smuzhiyun return ERR_NOT_ERASED;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun /*
264*4882a593Smuzhiyun * Disable interrupts which might cause a timeout
265*4882a593Smuzhiyun * here. Remember that our exception vectors are
266*4882a593Smuzhiyun * at address 0 in the flash, and we don't want a
267*4882a593Smuzhiyun * (ticker) exception to happen while the flash
268*4882a593Smuzhiyun * chip is in programming mode.
269*4882a593Smuzhiyun */
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun cflag = icache_status ();
272*4882a593Smuzhiyun icache_disable ();
273*4882a593Smuzhiyun iflag = disable_interrupts ();
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun MEM_FLASH_ADDR1 = CMD_UNLOCK1;
276*4882a593Smuzhiyun MEM_FLASH_ADDR2 = CMD_UNLOCK2;
277*4882a593Smuzhiyun MEM_FLASH_ADDR1 = CMD_PROGRAM;
278*4882a593Smuzhiyun *addr = data;
279*4882a593Smuzhiyun
280*4882a593Smuzhiyun /* arm simple, non interrupt dependent timer */
281*4882a593Smuzhiyun start = get_timer(0);
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun /* wait until flash is ready */
284*4882a593Smuzhiyun chip1 = 0;
285*4882a593Smuzhiyun do {
286*4882a593Smuzhiyun result = *addr;
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun /* check timeout */
289*4882a593Smuzhiyun if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
290*4882a593Smuzhiyun chip1 = ERR | TMO;
291*4882a593Smuzhiyun break;
292*4882a593Smuzhiyun }
293*4882a593Smuzhiyun if (!chip1 && ((result & 0x80) == (data & 0x80)))
294*4882a593Smuzhiyun chip1 = READY;
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun } while (!chip1);
297*4882a593Smuzhiyun
298*4882a593Smuzhiyun *addr = CMD_READ_ARRAY;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun if (chip1 == ERR || *addr != data)
301*4882a593Smuzhiyun rc = ERR_PROG_ERROR;
302*4882a593Smuzhiyun
303*4882a593Smuzhiyun if (iflag)
304*4882a593Smuzhiyun enable_interrupts ();
305*4882a593Smuzhiyun
306*4882a593Smuzhiyun if (cflag)
307*4882a593Smuzhiyun icache_enable ();
308*4882a593Smuzhiyun
309*4882a593Smuzhiyun return rc;
310*4882a593Smuzhiyun }
311*4882a593Smuzhiyun
312*4882a593Smuzhiyun
write_buff(flash_info_t * info,uchar * src,ulong addr,ulong cnt)313*4882a593Smuzhiyun int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun ulong wp, data;
316*4882a593Smuzhiyun int rc;
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun if (addr & 1) {
319*4882a593Smuzhiyun printf ("unaligned destination not supported\n");
320*4882a593Smuzhiyun return ERR_ALIGN;
321*4882a593Smuzhiyun }
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun #if 0
324*4882a593Smuzhiyun if (cnt & 1) {
325*4882a593Smuzhiyun printf ("odd transfer sizes not supported\n");
326*4882a593Smuzhiyun return ERR_ALIGN;
327*4882a593Smuzhiyun }
328*4882a593Smuzhiyun #endif
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun wp = addr;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun if (addr & 1) {
333*4882a593Smuzhiyun data = (*((volatile u8 *) addr) << 8) | *((volatile u8 *)
334*4882a593Smuzhiyun src);
335*4882a593Smuzhiyun if ((rc = write_word (info, wp - 1, data)) != 0) {
336*4882a593Smuzhiyun return (rc);
337*4882a593Smuzhiyun }
338*4882a593Smuzhiyun src += 1;
339*4882a593Smuzhiyun wp += 1;
340*4882a593Smuzhiyun cnt -= 1;
341*4882a593Smuzhiyun }
342*4882a593Smuzhiyun
343*4882a593Smuzhiyun while (cnt >= 2) {
344*4882a593Smuzhiyun data = *((volatile u16 *) src);
345*4882a593Smuzhiyun if ((rc = write_word (info, wp, data)) != 0) {
346*4882a593Smuzhiyun return (rc);
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun src += 2;
349*4882a593Smuzhiyun wp += 2;
350*4882a593Smuzhiyun cnt -= 2;
351*4882a593Smuzhiyun }
352*4882a593Smuzhiyun
353*4882a593Smuzhiyun if (cnt == 1) {
354*4882a593Smuzhiyun data = (*((volatile u8 *) src) << 8) |
355*4882a593Smuzhiyun *((volatile u8 *) (wp + 1));
356*4882a593Smuzhiyun if ((rc = write_word (info, wp, data)) != 0) {
357*4882a593Smuzhiyun return (rc);
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun src += 1;
360*4882a593Smuzhiyun wp += 1;
361*4882a593Smuzhiyun cnt -= 1;
362*4882a593Smuzhiyun }
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun return ERR_OK;
365*4882a593Smuzhiyun }
366