1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2012
3*4882a593Smuzhiyun * David Purdy <david.c.purdy@gmail.com>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on Kirkwood support:
6*4882a593Smuzhiyun * (C) Copyright 2009
7*4882a593Smuzhiyun * Marvell Semiconductor <www.marvell.com>
8*4882a593Smuzhiyun * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <common.h>
14*4882a593Smuzhiyun #include <miiphy.h>
15*4882a593Smuzhiyun #include <asm/arch/cpu.h>
16*4882a593Smuzhiyun #include <asm/arch/soc.h>
17*4882a593Smuzhiyun #include <asm/arch/mpp.h>
18*4882a593Smuzhiyun #include "pogo_e02.h"
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
21*4882a593Smuzhiyun
board_early_init_f(void)22*4882a593Smuzhiyun int board_early_init_f(void)
23*4882a593Smuzhiyun {
24*4882a593Smuzhiyun /*
25*4882a593Smuzhiyun * default gpio configuration
26*4882a593Smuzhiyun * There are maximum 64 gpios controlled through 2 sets of registers
27*4882a593Smuzhiyun * the below configuration configures mainly initial LED status
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
30*4882a593Smuzhiyun POGO_E02_OE_VAL_HIGH,
31*4882a593Smuzhiyun POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Multi-Purpose Pins Functionality configuration */
34*4882a593Smuzhiyun static const u32 kwmpp_config[] = {
35*4882a593Smuzhiyun MPP0_NF_IO2,
36*4882a593Smuzhiyun MPP1_NF_IO3,
37*4882a593Smuzhiyun MPP2_NF_IO4,
38*4882a593Smuzhiyun MPP3_NF_IO5,
39*4882a593Smuzhiyun MPP4_NF_IO6,
40*4882a593Smuzhiyun MPP5_NF_IO7,
41*4882a593Smuzhiyun MPP6_SYSRST_OUTn,
42*4882a593Smuzhiyun MPP7_GPO,
43*4882a593Smuzhiyun MPP8_UART0_RTS,
44*4882a593Smuzhiyun MPP9_UART0_CTS,
45*4882a593Smuzhiyun MPP10_UART0_TXD,
46*4882a593Smuzhiyun MPP11_UART0_RXD,
47*4882a593Smuzhiyun MPP12_SD_CLK,
48*4882a593Smuzhiyun MPP13_SD_CMD,
49*4882a593Smuzhiyun MPP14_SD_D0,
50*4882a593Smuzhiyun MPP15_SD_D1,
51*4882a593Smuzhiyun MPP16_SD_D2,
52*4882a593Smuzhiyun MPP17_SD_D3,
53*4882a593Smuzhiyun MPP18_NF_IO0,
54*4882a593Smuzhiyun MPP19_NF_IO1,
55*4882a593Smuzhiyun MPP29_TSMP9, /* USB Power Enable */
56*4882a593Smuzhiyun MPP48_GPIO, /* LED green */
57*4882a593Smuzhiyun MPP49_GPIO, /* LED orange */
58*4882a593Smuzhiyun 0
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun kirkwood_mpp_conf(kwmpp_config, NULL);
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
board_init(void)64*4882a593Smuzhiyun int board_init(void)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun /* Boot parameters address */
67*4882a593Smuzhiyun gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #ifdef CONFIG_RESET_PHY_R
73*4882a593Smuzhiyun /* Configure and initialize PHY */
reset_phy(void)74*4882a593Smuzhiyun void reset_phy(void)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun u16 reg;
77*4882a593Smuzhiyun u16 devadr;
78*4882a593Smuzhiyun char *name = "egiga0";
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun if (miiphy_set_current_dev(name))
81*4882a593Smuzhiyun return;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* command to read PHY dev address */
84*4882a593Smuzhiyun if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
85*4882a593Smuzhiyun printf("Err..(%s) could not read PHY dev address\n", __func__);
86*4882a593Smuzhiyun return;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /*
90*4882a593Smuzhiyun * Enable RGMII delay on Tx and Rx for CPU port
91*4882a593Smuzhiyun * Ref: sec 4.7.2 of chip datasheet
92*4882a593Smuzhiyun */
93*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
94*4882a593Smuzhiyun miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
95*4882a593Smuzhiyun reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
96*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
97*4882a593Smuzhiyun miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* reset the phy */
100*4882a593Smuzhiyun miiphy_reset(name, devadr);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun debug("88E1116 Initialized on %s\n", name);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun #endif /* CONFIG_RESET_PHY_R */
105