1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * SPL specific code for CCV xPress
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <common.h>
10*4882a593Smuzhiyun #include <spl.h>
11*4882a593Smuzhiyun #include <asm/io.h>
12*4882a593Smuzhiyun #include <asm/arch/mx6-ddr.h>
13*4882a593Smuzhiyun #include <asm/arch/crm_regs.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun /* Configuration for IM IME1G16D3EEBG-15EI, 64M x 16 -> 128MiB */
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
18*4882a593Smuzhiyun .grp_addds = 0x00000030,
19*4882a593Smuzhiyun .grp_ddrmode_ctl = 0x00020000,
20*4882a593Smuzhiyun .grp_b0ds = 0x00000030,
21*4882a593Smuzhiyun .grp_ctlds = 0x00000030,
22*4882a593Smuzhiyun .grp_b1ds = 0x00000030,
23*4882a593Smuzhiyun .grp_ddrpke = 0x00000000,
24*4882a593Smuzhiyun .grp_ddrmode = 0x00020000,
25*4882a593Smuzhiyun .grp_ddr_type = 0x000c0000,
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
29*4882a593Smuzhiyun .dram_dqm0 = 0x00000030,
30*4882a593Smuzhiyun .dram_dqm1 = 0x00000030,
31*4882a593Smuzhiyun .dram_ras = 0x00000030,
32*4882a593Smuzhiyun .dram_cas = 0x00000030,
33*4882a593Smuzhiyun .dram_odt0 = 0x00000030,
34*4882a593Smuzhiyun .dram_odt1 = 0x00000030,
35*4882a593Smuzhiyun .dram_sdba2 = 0x00000000,
36*4882a593Smuzhiyun .dram_sdclk_0 = 0x00000008,
37*4882a593Smuzhiyun .dram_sdqs0 = 0x00000038,
38*4882a593Smuzhiyun .dram_sdqs1 = 0x00000030,
39*4882a593Smuzhiyun .dram_reset = 0x00000030,
40*4882a593Smuzhiyun };
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static struct mx6_mmdc_calibration mx6_mmcd_calib = {
43*4882a593Smuzhiyun .p0_mpwldectrl0 = 0x00000000,
44*4882a593Smuzhiyun .p0_mpdgctrl0 = 0x4164015C,
45*4882a593Smuzhiyun .p0_mprddlctl = 0x40404446,
46*4882a593Smuzhiyun .p0_mpwrdlctl = 0x40405A52,
47*4882a593Smuzhiyun };
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun struct mx6_ddr_sysinfo ddr_sysinfo = {
50*4882a593Smuzhiyun .dsize = 0,
51*4882a593Smuzhiyun .cs_density = 20,
52*4882a593Smuzhiyun .ncs = 1,
53*4882a593Smuzhiyun .cs1_mirror = 0,
54*4882a593Smuzhiyun .rtt_wr = 2,
55*4882a593Smuzhiyun .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
56*4882a593Smuzhiyun .walat = 1, /* Write additional latency */
57*4882a593Smuzhiyun .ralat = 5, /* Read additional latency */
58*4882a593Smuzhiyun .mif3_mode = 3, /* Command prediction working mode */
59*4882a593Smuzhiyun .bi_on = 1, /* Bank interleaving enabled */
60*4882a593Smuzhiyun .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
61*4882a593Smuzhiyun .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
62*4882a593Smuzhiyun .ddr_type = DDR_TYPE_DDR3,
63*4882a593Smuzhiyun .refsel = 1, /* Refresh cycles at 32KHz */
64*4882a593Smuzhiyun .refr = 7, /* 8 refresh commands per refresh cycle */
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun static struct mx6_ddr3_cfg mem_ddr = {
68*4882a593Smuzhiyun .mem_speed = 800,
69*4882a593Smuzhiyun .density = 4,
70*4882a593Smuzhiyun .width = 16,
71*4882a593Smuzhiyun .banks = 8,
72*4882a593Smuzhiyun .rowaddr = 13,
73*4882a593Smuzhiyun .coladdr = 10,
74*4882a593Smuzhiyun .pagesz = 2,
75*4882a593Smuzhiyun .trcd = 1375,
76*4882a593Smuzhiyun .trcmin = 4875,
77*4882a593Smuzhiyun .trasmin = 3500,
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
ccgr_init(void)80*4882a593Smuzhiyun static void ccgr_init(void)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR0);
85*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR1);
86*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR2);
87*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR3);
88*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR4);
89*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR5);
90*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR6);
91*4882a593Smuzhiyun writel(0xFFFFFFFF, &ccm->CCGR7);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
spl_dram_init(void)94*4882a593Smuzhiyun static void spl_dram_init(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
97*4882a593Smuzhiyun mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
board_init_f(ulong dummy)100*4882a593Smuzhiyun void board_init_f(ulong dummy)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun /* Setup AIPS and disable watchdog */
103*4882a593Smuzhiyun arch_cpu_init();
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun ccgr_init();
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /* Setup iomux and i2c */
108*4882a593Smuzhiyun board_early_init_f();
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun /* Setup GP timer */
111*4882a593Smuzhiyun timer_init();
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun /* UART clocks enabled and gd valid - init serial console */
114*4882a593Smuzhiyun preloader_console_init();
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun /* DDR initialization */
117*4882a593Smuzhiyun spl_dram_init();
118*4882a593Smuzhiyun }
119