1*4882a593Smuzhiyun /**
2*4882a593Smuzhiyun * (C) Copyright 2014, Cavium Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun **/
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <common.h>
8*4882a593Smuzhiyun #include <dm.h>
9*4882a593Smuzhiyun #include <malloc.h>
10*4882a593Smuzhiyun #include <errno.h>
11*4882a593Smuzhiyun #include <linux/compiler.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <cavium/atf.h>
14*4882a593Smuzhiyun #include <asm/armv8/mmu.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #if !CONFIG_IS_ENABLED(OF_CONTROL)
17*4882a593Smuzhiyun #include <dm/platform_data/serial_pl01x.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static const struct pl01x_serial_platdata serial0 = {
20*4882a593Smuzhiyun .base = CONFIG_SYS_SERIAL0,
21*4882a593Smuzhiyun .type = TYPE_PL011,
22*4882a593Smuzhiyun .clock = 0,
23*4882a593Smuzhiyun .skip_init = true,
24*4882a593Smuzhiyun };
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun U_BOOT_DEVICE(thunderx_serial0) = {
27*4882a593Smuzhiyun .name = "serial_pl01x",
28*4882a593Smuzhiyun .platdata = &serial0,
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static const struct pl01x_serial_platdata serial1 = {
32*4882a593Smuzhiyun .base = CONFIG_SYS_SERIAL1,
33*4882a593Smuzhiyun .type = TYPE_PL011,
34*4882a593Smuzhiyun .clock = 0,
35*4882a593Smuzhiyun .skip_init = true,
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun U_BOOT_DEVICE(thunderx_serial1) = {
39*4882a593Smuzhiyun .name = "serial_pl01x",
40*4882a593Smuzhiyun .platdata = &serial1,
41*4882a593Smuzhiyun };
42*4882a593Smuzhiyun #endif
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun static struct mm_region thunderx_mem_map[] = {
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun .virt = 0x000000000000UL,
49*4882a593Smuzhiyun .phys = 0x000000000000UL,
50*4882a593Smuzhiyun .size = 0x40000000000UL,
51*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE,
52*4882a593Smuzhiyun }, {
53*4882a593Smuzhiyun .virt = 0x800000000000UL,
54*4882a593Smuzhiyun .phys = 0x800000000000UL,
55*4882a593Smuzhiyun .size = 0x40000000000UL,
56*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
57*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE,
58*4882a593Smuzhiyun }, {
59*4882a593Smuzhiyun .virt = 0x840000000000UL,
60*4882a593Smuzhiyun .phys = 0x840000000000UL,
61*4882a593Smuzhiyun .size = 0x40000000000UL,
62*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
63*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE,
64*4882a593Smuzhiyun }, {
65*4882a593Smuzhiyun /* List terminator */
66*4882a593Smuzhiyun 0,
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct mm_region *mem_map = thunderx_mem_map;
71*4882a593Smuzhiyun
board_init(void)72*4882a593Smuzhiyun int board_init(void)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun return 0;
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
timer_init(void)77*4882a593Smuzhiyun int timer_init(void)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun return 0;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
dram_init(void)82*4882a593Smuzhiyun int dram_init(void)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun ssize_t node_count = atf_node_count();
85*4882a593Smuzhiyun ssize_t dram_size;
86*4882a593Smuzhiyun int node;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun printf("Initializing\nNodes in system: %zd\n", node_count);
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun gd->ram_size = 0;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun for (node = 0; node < node_count; node++) {
93*4882a593Smuzhiyun dram_size = atf_dram_size(node);
94*4882a593Smuzhiyun printf("Node %d: %zd MBytes of DRAM\n", node, dram_size >> 20);
95*4882a593Smuzhiyun gd->ram_size += dram_size;
96*4882a593Smuzhiyun }
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun gd->ram_size -= MEM_BASE;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun *(unsigned long *)CPU_RELEASE_ADDR = 0;
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun puts("DRAM size:");
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun return 0;
105*4882a593Smuzhiyun }
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun /*
108*4882a593Smuzhiyun * Board specific reset that is system reset.
109*4882a593Smuzhiyun */
reset_cpu(ulong addr)110*4882a593Smuzhiyun void reset_cpu(ulong addr)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun }
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /*
115*4882a593Smuzhiyun * Board specific ethernet initialization routine.
116*4882a593Smuzhiyun */
board_eth_init(bd_t * bis)117*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun int rc = 0;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun return rc;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #ifdef CONFIG_PCI
pci_init_board(void)125*4882a593Smuzhiyun void pci_init_board(void)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun printf("DEBUG: PCI Init TODO *****\n");
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun #endif
130