1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007-2013
3*4882a593Smuzhiyun * Stelian Pop <stelian.pop@leadtechdesign.com>
4*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com>
5*4882a593Smuzhiyun * Thomas Petazzoni, Free Electrons, <thomas.petazzoni@free-electrons.com>
6*4882a593Smuzhiyun * Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <asm/arch/at91sam9_smc.h>
13*4882a593Smuzhiyun #include <asm/arch/at91_common.h>
14*4882a593Smuzhiyun #include <asm/arch/at91_matrix.h>
15*4882a593Smuzhiyun #include <asm/arch/clk.h>
16*4882a593Smuzhiyun #include <asm/arch/gpio.h>
17*4882a593Smuzhiyun #include <asm-generic/gpio.h>
18*4882a593Smuzhiyun #include <asm/io.h>
19*4882a593Smuzhiyun #include <net.h>
20*4882a593Smuzhiyun #include <netdev.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND
usb_a9263_nand_hw_init(void)25*4882a593Smuzhiyun static void usb_a9263_nand_hw_init(void)
26*4882a593Smuzhiyun {
27*4882a593Smuzhiyun unsigned long csa;
28*4882a593Smuzhiyun at91_smc_t *smc = (at91_smc_t *)ATMEL_BASE_SMC0;
29*4882a593Smuzhiyun at91_matrix_t *matrix = (at91_matrix_t *)ATMEL_BASE_MATRIX;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* Enable CS3 */
32*4882a593Smuzhiyun csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
33*4882a593Smuzhiyun writel(csa, &matrix->csa[0]);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Configure SMC CS3 for NAND/SmartMedia */
36*4882a593Smuzhiyun writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
37*4882a593Smuzhiyun AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
38*4882a593Smuzhiyun &smc->cs[3].setup);
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
41*4882a593Smuzhiyun AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
42*4882a593Smuzhiyun &smc->cs[3].pulse);
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
45*4882a593Smuzhiyun &smc->cs[3].cycle);
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
48*4882a593Smuzhiyun AT91_SMC_MODE_EXNW_DISABLE |
49*4882a593Smuzhiyun AT91_SMC_MODE_DBW_8 |
50*4882a593Smuzhiyun AT91_SMC_MODE_TDF_CYCLE(2), &smc->cs[3].mode);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_PIOA);
53*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_PIOCDE);
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun /* Configure RDY/BSY */
56*4882a593Smuzhiyun gpio_request(CONFIG_SYS_NAND_READY_PIN, "NAND ready/busy");
57*4882a593Smuzhiyun gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /* Enable NandFlash */
60*4882a593Smuzhiyun gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "NAND enable");
61*4882a593Smuzhiyun gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #ifdef CONFIG_MACB
usb_a9263_macb_hw_init(void)66*4882a593Smuzhiyun static void usb_a9263_macb_hw_init(void)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_EMAC);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /*
71*4882a593Smuzhiyun * Disable pull-up on:
72*4882a593Smuzhiyun * RXDV (PC25) => PHY normal mode (not Test mode)
73*4882a593Smuzhiyun * ERX0 (PE25) => PHY ADDR0
74*4882a593Smuzhiyun * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
75*4882a593Smuzhiyun *
76*4882a593Smuzhiyun * PHY has internal weak pull-up/pull-down
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun gpio_request(GPIO_PIN_PC(25), "PHY mode");
79*4882a593Smuzhiyun gpio_direction_input(GPIO_PIN_PC(25));
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun gpio_request(GPIO_PIN_PE(25), "PHY ADDR0");
82*4882a593Smuzhiyun gpio_direction_input(GPIO_PIN_PE(25));
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun gpio_request(GPIO_PIN_PE(26), "PHY ADDR1");
85*4882a593Smuzhiyun gpio_direction_input(GPIO_PIN_PE(26));
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun at91_phy_reset();
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* It will set proper pinmux for ports PC25, PE25-26 */
90*4882a593Smuzhiyun at91_macb_hw_init();
91*4882a593Smuzhiyun }
92*4882a593Smuzhiyun #endif
93*4882a593Smuzhiyun
board_init(void)94*4882a593Smuzhiyun int board_init(void)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun /* adress of boot parameters */
97*4882a593Smuzhiyun gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND
100*4882a593Smuzhiyun usb_a9263_nand_hw_init();
101*4882a593Smuzhiyun #endif
102*4882a593Smuzhiyun #ifdef CONFIG_MACB
103*4882a593Smuzhiyun usb_a9263_macb_hw_init();
104*4882a593Smuzhiyun #endif
105*4882a593Smuzhiyun #ifdef CONFIG_USB_OHCI_NEW
106*4882a593Smuzhiyun at91_uhp_hw_init();
107*4882a593Smuzhiyun #endif
108*4882a593Smuzhiyun return 0;
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun
dram_init(void)111*4882a593Smuzhiyun int dram_init(void)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
114*4882a593Smuzhiyun CONFIG_SYS_SDRAM_SIZE);
115*4882a593Smuzhiyun return 0;
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
board_eth_init(bd_t * bis)118*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun int rc = 0;
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun #ifdef CONFIG_MACB
123*4882a593Smuzhiyun rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x0001);
124*4882a593Smuzhiyun #endif
125*4882a593Smuzhiyun return rc;
126*4882a593Smuzhiyun }
127