1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2007 - 2013 Tensilica Inc.
3*4882a593Smuzhiyun * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <common.h>
9*4882a593Smuzhiyun #include <command.h>
10*4882a593Smuzhiyun #include <dm.h>
11*4882a593Smuzhiyun #include <dm/platform_data/net_ethoc.h>
12*4882a593Smuzhiyun #include <linux/ctype.h>
13*4882a593Smuzhiyun #include <linux/string.h>
14*4882a593Smuzhiyun #include <linux/stringify.h>
15*4882a593Smuzhiyun #include <asm/global_data.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /*
20*4882a593Smuzhiyun * Check board idendity.
21*4882a593Smuzhiyun * (Print information about the board to stdout.)
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #if defined(CONFIG_XTFPGA_LX60)
26*4882a593Smuzhiyun const char *board = "XT_AV60";
27*4882a593Smuzhiyun const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
28*4882a593Smuzhiyun #elif defined(CONFIG_XTFPGA_LX110)
29*4882a593Smuzhiyun const char *board = "XT_AV110";
30*4882a593Smuzhiyun const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
31*4882a593Smuzhiyun #elif defined(CONFIG_XTFPGA_LX200)
32*4882a593Smuzhiyun const char *board = "XT_AV200";
33*4882a593Smuzhiyun const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
34*4882a593Smuzhiyun #elif defined(CONFIG_XTFPGA_ML605)
35*4882a593Smuzhiyun const char *board = "XT_ML605";
36*4882a593Smuzhiyun const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
37*4882a593Smuzhiyun #elif defined(CONFIG_XTFPGA_KC705)
38*4882a593Smuzhiyun const char *board = "XT_KC705";
39*4882a593Smuzhiyun const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
40*4882a593Smuzhiyun #else
41*4882a593Smuzhiyun const char *board = "<unknown>";
42*4882a593Smuzhiyun const char *description = "";
43*4882a593Smuzhiyun #endif
44*4882a593Smuzhiyun
checkboard(void)45*4882a593Smuzhiyun int checkboard(void)
46*4882a593Smuzhiyun {
47*4882a593Smuzhiyun printf("Board: %s: %sTensilica bitstream\n", board, description);
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
dram_init_banksize(void)51*4882a593Smuzhiyun int dram_init_banksize(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun gd->bd->bi_memstart = PHYSADDR(CONFIG_SYS_SDRAM_BASE);
54*4882a593Smuzhiyun gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return 0;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
board_postclk_init(void)59*4882a593Smuzhiyun int board_postclk_init(void)
60*4882a593Smuzhiyun {
61*4882a593Smuzhiyun /*
62*4882a593Smuzhiyun * Obtain CPU clock frequency from board and cache in global
63*4882a593Smuzhiyun * data structure (Hz). Return 0 on success (OK to continue),
64*4882a593Smuzhiyun * else non-zero (hang).
65*4882a593Smuzhiyun */
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun #ifdef CONFIG_SYS_FPGAREG_FREQ
68*4882a593Smuzhiyun gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
69*4882a593Smuzhiyun #else
70*4882a593Smuzhiyun /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
71*4882a593Smuzhiyun gd->cpu_clk = 50000000UL;
72*4882a593Smuzhiyun #endif
73*4882a593Smuzhiyun return 0;
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /*
77*4882a593Smuzhiyun * Miscellaneous late initializations.
78*4882a593Smuzhiyun * The environment has been set up, so we can set the Ethernet address.
79*4882a593Smuzhiyun */
80*4882a593Smuzhiyun
misc_init_r(void)81*4882a593Smuzhiyun int misc_init_r(void)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun #ifdef CONFIG_CMD_NET
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun * Initialize ethernet environment variables and board info.
86*4882a593Smuzhiyun * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
87*4882a593Smuzhiyun */
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun char *s = env_get("ethaddr");
90*4882a593Smuzhiyun if (s == 0) {
91*4882a593Smuzhiyun unsigned int x;
92*4882a593Smuzhiyun char s[] = __stringify(CONFIG_ETHBASE);
93*4882a593Smuzhiyun x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
94*4882a593Smuzhiyun & FPGAREG_MAC_MASK;
95*4882a593Smuzhiyun sprintf(&s[15], "%02x", x);
96*4882a593Smuzhiyun env_set("ethaddr", s);
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun #endif /* CONFIG_CMD_NET */
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun return 0;
101*4882a593Smuzhiyun }
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun U_BOOT_DEVICE(sysreset) = {
104*4882a593Smuzhiyun .name = "xtfpga_sysreset",
105*4882a593Smuzhiyun };
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static struct ethoc_eth_pdata ethoc_pdata = {
108*4882a593Smuzhiyun .eth_pdata = {
109*4882a593Smuzhiyun .iobase = CONFIG_SYS_ETHOC_BASE,
110*4882a593Smuzhiyun },
111*4882a593Smuzhiyun .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun U_BOOT_DEVICE(ethoc) = {
115*4882a593Smuzhiyun .name = "ethoc",
116*4882a593Smuzhiyun .platdata = ðoc_pdata,
117*4882a593Smuzhiyun };
118