1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * (C) Copyright 2016 Broadcom Ltd.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun #include <common.h>
7*4882a593Smuzhiyun #include <asm/system.h>
8*4882a593Smuzhiyun #include <asm/armv8/mmu.h>
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun static struct mm_region ns2_mem_map[] = {
11*4882a593Smuzhiyun {
12*4882a593Smuzhiyun .virt = 0x0UL,
13*4882a593Smuzhiyun .phys = 0x0UL,
14*4882a593Smuzhiyun .size = 0x80000000UL,
15*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
16*4882a593Smuzhiyun PTE_BLOCK_NON_SHARE |
17*4882a593Smuzhiyun PTE_BLOCK_PXN | PTE_BLOCK_UXN
18*4882a593Smuzhiyun }, {
19*4882a593Smuzhiyun .virt = 0x80000000UL,
20*4882a593Smuzhiyun .phys = 0x80000000UL,
21*4882a593Smuzhiyun .size = 0xff80000000UL,
22*4882a593Smuzhiyun .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
23*4882a593Smuzhiyun PTE_BLOCK_INNER_SHARE
24*4882a593Smuzhiyun }, {
25*4882a593Smuzhiyun /* List terminator */
26*4882a593Smuzhiyun 0,
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun struct mm_region *mem_map = ns2_mem_map;
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
33*4882a593Smuzhiyun
board_init(void)34*4882a593Smuzhiyun int board_init(void)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun return 0;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
dram_init(void)39*4882a593Smuzhiyun int dram_init(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
42*4882a593Smuzhiyun PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE);
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
dram_init_banksize(void)46*4882a593Smuzhiyun int dram_init_banksize(void)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
49*4882a593Smuzhiyun gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + PHYS_SDRAM_1_SIZE;
52*4882a593Smuzhiyun gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun return 0;
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
reset_cpu(ulong addr)57*4882a593Smuzhiyun void reset_cpu(ulong addr)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun psci_system_reset();
60*4882a593Smuzhiyun }
61