1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * board.h
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2016
5*4882a593Smuzhiyun * Heiko Schocher, DENX Software Engineering, hs@denx.de.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on:
8*4882a593Smuzhiyun * TI AM335x boards information header
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
11*4882a593Smuzhiyun *
12*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
13*4882a593Smuzhiyun */
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #ifndef _BOARD_H_
16*4882a593Smuzhiyun #define _BOARD_H_
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /* Definition to control the GPIOs (for LEDs and Reset) */
19*4882a593Smuzhiyun #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
20*4882a593Smuzhiyun
board_is_b_sample(void)21*4882a593Smuzhiyun static inline int board_is_b_sample(void)
22*4882a593Smuzhiyun {
23*4882a593Smuzhiyun #if defined CONFIG_B_SAMPLE
24*4882a593Smuzhiyun return 1;
25*4882a593Smuzhiyun #else
26*4882a593Smuzhiyun return 0;
27*4882a593Smuzhiyun #endif
28*4882a593Smuzhiyun }
29*4882a593Smuzhiyun
board_is_c_sample(void)30*4882a593Smuzhiyun static inline int board_is_c_sample(void)
31*4882a593Smuzhiyun {
32*4882a593Smuzhiyun #if defined CONFIG_C_SAMPLE
33*4882a593Smuzhiyun return 1;
34*4882a593Smuzhiyun #else
35*4882a593Smuzhiyun return 0;
36*4882a593Smuzhiyun #endif
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
board_is_c3_sample(void)39*4882a593Smuzhiyun static inline int board_is_c3_sample(void)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun #if defined CONFIG_C3_SAMPLE
42*4882a593Smuzhiyun return 1;
43*4882a593Smuzhiyun #else
44*4882a593Smuzhiyun return 0;
45*4882a593Smuzhiyun #endif
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun
board_is_series(void)48*4882a593Smuzhiyun static inline int board_is_series(void)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun #if defined CONFIG_SERIES
51*4882a593Smuzhiyun return 1;
52*4882a593Smuzhiyun #else
53*4882a593Smuzhiyun return 0;
54*4882a593Smuzhiyun #endif
55*4882a593Smuzhiyun }
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun /*
58*4882a593Smuzhiyun * Definitions for pinmuxing header and Board ID strings
59*4882a593Smuzhiyun */
60*4882a593Smuzhiyun #if defined CONFIG_B_SAMPLE
61*4882a593Smuzhiyun # define BOARD_ID_STR "SHC B-Sample\n"
62*4882a593Smuzhiyun #elif defined CONFIG_B2_SAMPLE
63*4882a593Smuzhiyun # define BOARD_ID_STR "SHC B2-Sample\n"
64*4882a593Smuzhiyun #elif defined CONFIG_C_SAMPLE
65*4882a593Smuzhiyun # if defined(CONFIG_SHC_NETBOOT)
66*4882a593Smuzhiyun # define BOARD_ID_STR "#### NETBOOT ####\nSHC C-Sample\n"
67*4882a593Smuzhiyun # elif defined(CONFIG_SHC_SDBOOT)
68*4882a593Smuzhiyun # define BOARD_ID_STR "#### SDBOOT ####\nSHC C-Sample\n"
69*4882a593Smuzhiyun # else
70*4882a593Smuzhiyun # define BOARD_ID_STR "SHC C-Sample\n"
71*4882a593Smuzhiyun # endif
72*4882a593Smuzhiyun #elif defined CONFIG_C2_SAMPLE
73*4882a593Smuzhiyun # if defined(CONFIG_SHC_ICT)
74*4882a593Smuzhiyun # define BOARD_ID_STR "#### ICT ####\nSHC C2-Sample\n"
75*4882a593Smuzhiyun # elif defined(CONFIG_SHC_NETBOOT)
76*4882a593Smuzhiyun # define BOARD_ID_STR "#### NETBOOT ####\nSHC C2-Sample\n"
77*4882a593Smuzhiyun # elif defined(CONFIG_SHC_SDBOOT)
78*4882a593Smuzhiyun # define BOARD_ID_STR "#### SDBOOT ####\nSHC C2-Sample\n"
79*4882a593Smuzhiyun # else
80*4882a593Smuzhiyun # define BOARD_ID_STR "SHC C2-Sample\n"
81*4882a593Smuzhiyun # endif
82*4882a593Smuzhiyun #elif defined CONFIG_C3_SAMPLE
83*4882a593Smuzhiyun # if defined(CONFIG_SHC_ICT)
84*4882a593Smuzhiyun # define BOARD_ID_STR "#### ICT ####\nSHC C3-Sample\n"
85*4882a593Smuzhiyun # elif defined(CONFIG_SHC_NETBOOT)
86*4882a593Smuzhiyun # define BOARD_ID_STR "#### NETBOOT ####\nSHC C3-Sample\n"
87*4882a593Smuzhiyun # elif defined(CONFIG_SHC_SDBOOT)
88*4882a593Smuzhiyun # define BOARD_ID_STR "#### SDBOOT ####\nSHC C3-Sample\n"
89*4882a593Smuzhiyun # else
90*4882a593Smuzhiyun # define BOARD_ID_STR "SHC C3-Sample\n"
91*4882a593Smuzhiyun # endif
92*4882a593Smuzhiyun #elif defined CONFIG_SERIES
93*4882a593Smuzhiyun # if defined(CONFIG_SHC_ICT)
94*4882a593Smuzhiyun # define BOARD_ID_STR "#### ICT ####\nSHC\n"
95*4882a593Smuzhiyun # elif defined(CONFIG_SHC_NETBOOT)
96*4882a593Smuzhiyun # define BOARD_ID_STR "#### NETBOOT ####\nSHC\n"
97*4882a593Smuzhiyun # elif defined(CONFIG_SHC_SDBOOT)
98*4882a593Smuzhiyun # define BOARD_ID_STR "#### SDBOOT ####\nSHC\n"
99*4882a593Smuzhiyun # else
100*4882a593Smuzhiyun # define BOARD_ID_STR "SHC\n"
101*4882a593Smuzhiyun # endif
102*4882a593Smuzhiyun #else
103*4882a593Smuzhiyun # define BOARD_ID_STR "Unknown device!\n"
104*4882a593Smuzhiyun #endif
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /*
107*4882a593Smuzhiyun * Definitions for GPIO pin assignments
108*4882a593Smuzhiyun */
109*4882a593Smuzhiyun #if defined CONFIG_B_SAMPLE
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun # define LED_PWR_BL_GPIO GPIO_TO_PIN(1, 17)
112*4882a593Smuzhiyun # define LED_PWR_RD_GPIO GPIO_TO_PIN(1, 18)
113*4882a593Smuzhiyun # define LED_PWR_GN_GPIO GPIO_TO_PIN(1, 19)
114*4882a593Smuzhiyun # define LED_CONN_BL_GPIO GPIO_TO_PIN(0, 26)
115*4882a593Smuzhiyun # define LED_CONN_RD_GPIO GPIO_TO_PIN(0, 22)
116*4882a593Smuzhiyun # define LED_CONN_GN_GPIO GPIO_TO_PIN(0, 23)
117*4882a593Smuzhiyun # define RESET_GPIO GPIO_TO_PIN(1, 29)
118*4882a593Smuzhiyun # define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16)
119*4882a593Smuzhiyun # define WIFI_RST_GPIO GPIO_TO_PIN(0, 27)
120*4882a593Smuzhiyun # define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18)
121*4882a593Smuzhiyun # define BIDCOS_RST_GPIO GPIO_TO_PIN(0, 12)
122*4882a593Smuzhiyun # define ENOC_RST_GPIO GPIO_TO_PIN(1, 22)
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun #else
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun # define LED_PWR_BL_GPIO GPIO_TO_PIN(0, 22)
127*4882a593Smuzhiyun # define LED_PWR_RD_GPIO GPIO_TO_PIN(0, 23)
128*4882a593Smuzhiyun # define LED_LAN_BL_GPIO GPIO_TO_PIN(1, 17)
129*4882a593Smuzhiyun # define LED_LAN_RD_GPIO GPIO_TO_PIN(0, 26)
130*4882a593Smuzhiyun # define LED_CLOUD_BL_GPIO GPIO_TO_PIN(1, 18)
131*4882a593Smuzhiyun # define LED_CLOUD_RD_GPIO GPIO_TO_PIN(2, 2)
132*4882a593Smuzhiyun # define LED_PWM_GPIO GPIO_TO_PIN(1, 19)
133*4882a593Smuzhiyun # define RESET_GPIO GPIO_TO_PIN(1, 29)
134*4882a593Smuzhiyun # define WIFI_REGEN_GPIO GPIO_TO_PIN(1, 16)
135*4882a593Smuzhiyun # define WIFI_RST_GPIO GPIO_TO_PIN(0, 27)
136*4882a593Smuzhiyun # define ZIGBEE_RST_GPIO GPIO_TO_PIN(3, 18)
137*4882a593Smuzhiyun # define BIDCOS_RST_GPIO GPIO_TO_PIN(1, 24)
138*4882a593Smuzhiyun # define Z_WAVE_RST_GPIO GPIO_TO_PIN(1, 21)
139*4882a593Smuzhiyun # define ENOC_RST_GPIO GPIO_TO_PIN(1, 22)
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun #endif
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun #define BACK_BUTTON_GPIO GPIO_TO_PIN(1, 29)
144*4882a593Smuzhiyun #define FRONT_BUTTON_GPIO GPIO_TO_PIN(1, 25)
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /* Reset is on GPIO pin 29 of GPIO bank 1 */
147*4882a593Smuzhiyun #define RESET_MASK (0x1 << 29)
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun #define HDR_MAGIC 0x43485342
150*4882a593Smuzhiyun #define HDR_ETH_ALEN 6
151*4882a593Smuzhiyun #define HDR_NAME_LEN 8
152*4882a593Smuzhiyun #define HDR_REV_LEN 8
153*4882a593Smuzhiyun #define HDR_SER_LEN 16
154*4882a593Smuzhiyun #define HDR_ROOT_LEN 12
155*4882a593Smuzhiyun #define HDR_FATC_LEN 12
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /*
158*4882a593Smuzhiyun * SHC parameters held in On-Board I²C EEPROM device.
159*4882a593Smuzhiyun *
160*4882a593Smuzhiyun * Header Format
161*4882a593Smuzhiyun *
162*4882a593Smuzhiyun * Name Size Contents
163*4882a593Smuzhiyun *-------------------------------------------------------------
164*4882a593Smuzhiyun * Magic 4 0x42 0x53 0x48 0x43 [BSHC]
165*4882a593Smuzhiyun *
166*4882a593Smuzhiyun * Version 2 0x0100 for v1.0
167*4882a593Smuzhiyun *
168*4882a593Smuzhiyun * Lenght 2 The length of the complete structure, not only this header
169*4882a593Smuzhiyun *
170*4882a593Smuzhiyun * Eth-MAC 6 Ethernet MAC Address
171*4882a593Smuzhiyun * SHC Pool: 7C:AC:B2:00:10:01 - TBD
172*4882a593Smuzhiyun *
173*4882a593Smuzhiyun * --- Further values follow, not important for Bootloader ---
174*4882a593Smuzhiyun */
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun struct shc_eeprom {
177*4882a593Smuzhiyun u32 magic;
178*4882a593Smuzhiyun u16 version;
179*4882a593Smuzhiyun u16 lenght;
180*4882a593Smuzhiyun uint8_t mac_addr[HDR_ETH_ALEN];
181*4882a593Smuzhiyun };
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun void enable_uart0_pin_mux(void);
184*4882a593Smuzhiyun void enable_shc_board_pin_mux(void);
185*4882a593Smuzhiyun void enable_shc_board_pwm_pin_mux(void);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #endif
188