1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Bluewater Systems Snapper 9260/9G20 modules
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * (C) Copyright 2011 Bluewater Systems
5*4882a593Smuzhiyun * Author: Andre Renaud <andre@bluewatersys.com>
6*4882a593Smuzhiyun * Author: Ryan Mallon <ryan@bluewatersys.com>
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <common.h>
12*4882a593Smuzhiyun #include <dm.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <asm/gpio.h>
15*4882a593Smuzhiyun #include <asm/mach-types.h>
16*4882a593Smuzhiyun #include <asm/arch/at91sam9260_matrix.h>
17*4882a593Smuzhiyun #include <asm/arch/at91sam9_smc.h>
18*4882a593Smuzhiyun #include <asm/arch/at91_common.h>
19*4882a593Smuzhiyun #include <asm/arch/clk.h>
20*4882a593Smuzhiyun #include <asm/arch/gpio.h>
21*4882a593Smuzhiyun #include <asm/arch/atmel_serial.h>
22*4882a593Smuzhiyun #include <net.h>
23*4882a593Smuzhiyun #include <netdev.h>
24*4882a593Smuzhiyun #include <i2c.h>
25*4882a593Smuzhiyun #include <pca953x.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /* IO Expander pins */
30*4882a593Smuzhiyun #define IO_EXP_ETH_RESET (0 << 1)
31*4882a593Smuzhiyun #define IO_EXP_ETH_POWER (1 << 1)
32*4882a593Smuzhiyun
macb_hw_init(void)33*4882a593Smuzhiyun static void macb_hw_init(void)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_EMAC0);
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Disable pull-ups to prevent PHY going into test mode */
40*4882a593Smuzhiyun writel(pin_to_mask(AT91_PIN_PA14) |
41*4882a593Smuzhiyun pin_to_mask(AT91_PIN_PA15) |
42*4882a593Smuzhiyun pin_to_mask(AT91_PIN_PA18),
43*4882a593Smuzhiyun &pioa->pudr);
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun /* Power down ethernet */
46*4882a593Smuzhiyun pca953x_set_dir(0x28, IO_EXP_ETH_POWER, PCA953X_DIR_OUT);
47*4882a593Smuzhiyun pca953x_set_val(0x28, IO_EXP_ETH_POWER, 1);
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Hold ethernet in reset */
50*4882a593Smuzhiyun pca953x_set_dir(0x28, IO_EXP_ETH_RESET, PCA953X_DIR_OUT);
51*4882a593Smuzhiyun pca953x_set_val(0x28, IO_EXP_ETH_RESET, 0);
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /* Enable ethernet power */
54*4882a593Smuzhiyun pca953x_set_val(0x28, IO_EXP_ETH_POWER, 0);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun at91_phy_reset();
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Bring the ethernet out of reset */
59*4882a593Smuzhiyun pca953x_set_val(0x28, IO_EXP_ETH_RESET, 1);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun /* The phy internal reset take 21ms */
62*4882a593Smuzhiyun udelay(21 * 1000);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Re-enable pull-up */
65*4882a593Smuzhiyun writel(pin_to_mask(AT91_PIN_PA14) |
66*4882a593Smuzhiyun pin_to_mask(AT91_PIN_PA15) |
67*4882a593Smuzhiyun pin_to_mask(AT91_PIN_PA18),
68*4882a593Smuzhiyun &pioa->puer);
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun at91_macb_hw_init();
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
nand_hw_init(void)73*4882a593Smuzhiyun static void nand_hw_init(void)
74*4882a593Smuzhiyun {
75*4882a593Smuzhiyun struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
76*4882a593Smuzhiyun struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
77*4882a593Smuzhiyun unsigned long csa;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /* Enable CS3 as NAND/SmartMedia */
80*4882a593Smuzhiyun csa = readl(&matrix->ebicsa);
81*4882a593Smuzhiyun csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
82*4882a593Smuzhiyun writel(csa, &matrix->ebicsa);
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /* Configure SMC CS3 for NAND/SmartMedia */
85*4882a593Smuzhiyun writel(AT91_SMC_SETUP_NWE(2) | AT91_SMC_SETUP_NCS_WR(0) |
86*4882a593Smuzhiyun AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(0),
87*4882a593Smuzhiyun &smc->cs[3].setup);
88*4882a593Smuzhiyun writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(4) |
89*4882a593Smuzhiyun AT91_SMC_PULSE_NRD(4) | AT91_SMC_PULSE_NCS_RD(4),
90*4882a593Smuzhiyun &smc->cs[3].pulse);
91*4882a593Smuzhiyun writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(7),
92*4882a593Smuzhiyun &smc->cs[3].cycle);
93*4882a593Smuzhiyun writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
94*4882a593Smuzhiyun AT91_SMC_MODE_EXNW_DISABLE |
95*4882a593Smuzhiyun AT91_SMC_MODE_DBW_8 |
96*4882a593Smuzhiyun AT91_SMC_MODE_TDF_CYCLE(3),
97*4882a593Smuzhiyun &smc->cs[3].mode);
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /* Configure RDY/BSY */
100*4882a593Smuzhiyun gpio_request(CONFIG_SYS_NAND_READY_PIN, "nand_rdy");
101*4882a593Smuzhiyun gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun /* Enable NandFlash */
104*4882a593Smuzhiyun gpio_request(CONFIG_SYS_NAND_ENABLE_PIN, "nand_ce");
105*4882a593Smuzhiyun gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
board_init(void)108*4882a593Smuzhiyun int board_init(void)
109*4882a593Smuzhiyun {
110*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_PIOA);
111*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_PIOB);
112*4882a593Smuzhiyun at91_periph_clk_enable(ATMEL_ID_PIOC);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun /* The mach-type is the same for both Snapper 9260 and 9G20 */
115*4882a593Smuzhiyun gd->bd->bi_arch_number = MACH_TYPE_SNAPPER_9260;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Address of boot parameters */
118*4882a593Smuzhiyun gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun /* Initialise peripherals */
121*4882a593Smuzhiyun at91_seriald_hw_init();
122*4882a593Smuzhiyun i2c_set_bus_num(0);
123*4882a593Smuzhiyun nand_hw_init();
124*4882a593Smuzhiyun macb_hw_init();
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun return 0;
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
board_eth_init(bd_t * bis)129*4882a593Smuzhiyun int board_eth_init(bd_t *bis)
130*4882a593Smuzhiyun {
131*4882a593Smuzhiyun return macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x1f);
132*4882a593Smuzhiyun }
133*4882a593Smuzhiyun
dram_init(void)134*4882a593Smuzhiyun int dram_init(void)
135*4882a593Smuzhiyun {
136*4882a593Smuzhiyun gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
137*4882a593Smuzhiyun CONFIG_SYS_SDRAM_SIZE);
138*4882a593Smuzhiyun return 0;
139*4882a593Smuzhiyun }
140*4882a593Smuzhiyun
reset_phy(void)141*4882a593Smuzhiyun void reset_phy(void)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static struct atmel_serial_platdata at91sam9260_serial_plat = {
146*4882a593Smuzhiyun .base_addr = ATMEL_BASE_DBGU,
147*4882a593Smuzhiyun };
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun U_BOOT_DEVICE(at91sam9260_serial) = {
150*4882a593Smuzhiyun .name = "serial_atmel",
151*4882a593Smuzhiyun .platdata = &at91sam9260_serial_plat,
152*4882a593Smuzhiyun };
153