1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Projectiondesign AS 3*4882a593Smuzhiyun * Derived from ./board/freescale/mx6qsabrelite/imximage.cfg 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * Jason Liu <r64343@freescale.com> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Refer doc/README.imximage for more details about how-to configure 11*4882a593Smuzhiyun * and create imximage boot image 12*4882a593Smuzhiyun * 13*4882a593Smuzhiyun * The syntax is taken as close as possible with the kwbimage 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/* image version */ 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunIMAGE_VERSION 2 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun/* 21*4882a593Smuzhiyun * Boot Device : one of 22*4882a593Smuzhiyun * sd, nand 23*4882a593Smuzhiyun */ 24*4882a593SmuzhiyunBOOT_FROM nand 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun/* 27*4882a593Smuzhiyun * Device Configuration Data (DCD) 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * Each entry must have the format: 30*4882a593Smuzhiyun * Addr-type Address Value 31*4882a593Smuzhiyun * 32*4882a593Smuzhiyun * where: 33*4882a593Smuzhiyun * Addr-type register length (1,2 or 4 bytes) 34*4882a593Smuzhiyun * Address absolute address of the register 35*4882a593Smuzhiyun * value value to be stored in the register 36*4882a593Smuzhiyun */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun#define __ASSEMBLY__ 39*4882a593Smuzhiyun#include <config.h> 40*4882a593Smuzhiyun#include "asm/arch/mx6-ddr.h" 41*4882a593Smuzhiyun#include "asm/arch/iomux.h" 42*4882a593Smuzhiyun#include "asm/arch/crm_regs.h" 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 45*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 46*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 47*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 48*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 49*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 50*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 51*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 52*4882a593Smuzhiyun 53*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM0, 0x00020030 54*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM1, 0x00020030 55*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM2, 0x00020030 56*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM3, 0x00020030 57*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM4, 0x00020030 58*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM5, 0x00020030 59*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM6, 0x00020030 60*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_DQM7, 0x00020030 61*4882a593Smuzhiyun 62*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_CAS, 0x00020030 63*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_RAS, 0x00020030 64*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00020030 65*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00020030 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_RESET, 0x00020030 68*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 69*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 74*4882a593SmuzhiyunDATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 75*4882a593Smuzhiyun 76*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B0DS, 0x00000030 77*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B1DS, 0x00000030 78*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B2DS, 0x00000030 79*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B3DS, 0x00000030 80*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B4DS, 0x00000030 81*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B5DS, 0x00000030 82*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B6DS, 0x00000030 83*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_B7DS, 0x00000030 84*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun/* (differential input) */ 87*4882a593SmuzhiyunDATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 88*4882a593Smuzhiyun/* disable ddr pullups */ 89*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 90*4882a593Smuzhiyun/* (differential input) */ 91*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 92*4882a593Smuzhiyun/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 93*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 94*4882a593Smuzhiyun/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ 95*4882a593SmuzhiyunDATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun/* Read data DQ Byte0-3 delay */ 98*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 99*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 100*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 101*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 102*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 103*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 104*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 105*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun/* 108*4882a593Smuzhiyun * MDMISC mirroring interleaved (row/bank/col) 109*4882a593Smuzhiyun */ 110*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 111*4882a593Smuzhiyun 112*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 113*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG0, 0x555A7975 114*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG1, 0xFF538E64 115*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 116*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 117*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOR, 0x005B0E21 118*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOTC, 0x09444040 119*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDPDC, 0x00025576 120*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDASP, 0x00000017 121*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCTL, 0x83190000 122*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04088032 123*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x0408803A 124*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 125*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x0000803B 126*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 127*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 128*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x09408030 129*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x09408038 130*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 131*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 132*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1380003 133*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1380003 134*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDREF, 0x00005800 135*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022227 136*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022227 137*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x434B0350 138*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x034C0359 139*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x434B0350 140*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x03650348 141*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4436383B 142*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x39393341 143*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x35373933 144*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x48254A36 145*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 146*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 147*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x00440044 148*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x00440044 149*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 150*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 151*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 152*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun/* set the default clock gate to save power */ 155*4882a593SmuzhiyunDATA 4, CCM_CCGR0, 0x00C03F3F 156*4882a593SmuzhiyunDATA 4, CCM_CCGR1, 0x0030FC03 157*4882a593SmuzhiyunDATA 4, CCM_CCGR2, 0x0FFFC000 158*4882a593SmuzhiyunDATA 4, CCM_CCGR3, 0x3FF00000 159*4882a593SmuzhiyunDATA 4, CCM_CCGR4, 0xFFFFF300 /* enable NAND/GPMI/BCH clocks */ 160*4882a593SmuzhiyunDATA 4, CCM_CCGR5, 0x0F0000C3 161*4882a593SmuzhiyunDATA 4, CCM_CCGR6, 0x000003FF 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun/* enable AXI cache for VDOA/VPU/IPU */ 164*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR4, 0xF00000CF 165*4882a593Smuzhiyun/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ 166*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR6, 0x007F007F 167*4882a593SmuzhiyunDATA 4, MX6_IOMUXC_GPR7, 0x007F007F 168