1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2010,2011 3*4882a593Smuzhiyun * NVIDIA Corporation <www.nvidia.com> 4*4882a593Smuzhiyun * (C) Copyright 2011-2012 5*4882a593Smuzhiyun * Avionic Design GmbH <www.avionic-design.de> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <common.h> 11*4882a593Smuzhiyun #include <ns16550.h> 12*4882a593Smuzhiyun #include <asm/io.h> 13*4882a593Smuzhiyun #include <asm/gpio.h> 14*4882a593Smuzhiyun #include <asm/arch/clock.h> 15*4882a593Smuzhiyun #include <asm/arch/funcmux.h> 16*4882a593Smuzhiyun #include <asm/arch/pinmux.h> 17*4882a593Smuzhiyun #include <asm/arch/tegra.h> 18*4882a593Smuzhiyun #include <asm/arch-tegra/board.h> 19*4882a593Smuzhiyun #include <asm/arch-tegra/clk_rst.h> 20*4882a593Smuzhiyun #include <asm/arch-tegra/sys_proto.h> 21*4882a593Smuzhiyun #include <asm/arch-tegra/uart.h> 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifdef CONFIG_BOARD_EARLY_INIT_F gpio_early_init(void)24*4882a593Smuzhiyunvoid gpio_early_init(void) 25*4882a593Smuzhiyun { 26*4882a593Smuzhiyun gpio_request(TEGRA_GPIO(I, 4), NULL); 27*4882a593Smuzhiyun gpio_direction_output(TEGRA_GPIO(I, 4), 1); 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun #endif 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #ifdef CONFIG_MMC_SDHCI_TEGRA 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * Routine: pin_mux_mmc 34*4882a593Smuzhiyun * Description: setup the pin muxes/tristate values for the SDMMC(s) 35*4882a593Smuzhiyun */ pin_mux_mmc(void)36*4882a593Smuzhiyunvoid pin_mux_mmc(void) 37*4882a593Smuzhiyun { 38*4882a593Smuzhiyun funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT); 39*4882a593Smuzhiyun /* for write-protect GPIO PI6 */ 40*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_ATA); 41*4882a593Smuzhiyun /* for CD GPIO PH2 */ 42*4882a593Smuzhiyun pinmux_tristate_disable(PMUX_PINGRP_ATD); 43*4882a593Smuzhiyun } 44*4882a593Smuzhiyun #endif 45