1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2013 3*4882a593Smuzhiyun * Avionic Design GmbH <www.avionic-design.de> 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_ 9*4882a593Smuzhiyun #define _PINMUX_CONFIG_TAMONTEN_NG_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \ 12*4882a593Smuzhiyun { \ 13*4882a593Smuzhiyun .pingrp = PMUX_PINGRP_##_pingrp, \ 14*4882a593Smuzhiyun .func = PMUX_FUNC_##_mux, \ 15*4882a593Smuzhiyun .pull = PMUX_PULL_##_pull, \ 16*4882a593Smuzhiyun .tristate = PMUX_TRI_##_tri, \ 17*4882a593Smuzhiyun .io = PMUX_PIN_##_io, \ 18*4882a593Smuzhiyun .lock = PMUX_PIN_LOCK_DEFAULT, \ 19*4882a593Smuzhiyun .od = PMUX_PIN_OD_DEFAULT, \ 20*4882a593Smuzhiyun .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 21*4882a593Smuzhiyun } 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \ 24*4882a593Smuzhiyun { \ 25*4882a593Smuzhiyun .pingrp = PMUX_PINGRP_##_pingrp, \ 26*4882a593Smuzhiyun .func = PMUX_FUNC_##_mux, \ 27*4882a593Smuzhiyun .pull = PMUX_PULL_##_pull, \ 28*4882a593Smuzhiyun .tristate = PMUX_TRI_##_tri, \ 29*4882a593Smuzhiyun .io = PMUX_PIN_##_io, \ 30*4882a593Smuzhiyun .lock = PMUX_PIN_LOCK_##_lock, \ 31*4882a593Smuzhiyun .od = PMUX_PIN_OD_##_od, \ 32*4882a593Smuzhiyun .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \ 33*4882a593Smuzhiyun } 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define LV_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \ 36*4882a593Smuzhiyun { \ 37*4882a593Smuzhiyun .pingrp = PMUX_PINGRP_##_pingrp, \ 38*4882a593Smuzhiyun .func = PMUX_FUNC_##_mux, \ 39*4882a593Smuzhiyun .pull = PMUX_PULL_##_pull, \ 40*4882a593Smuzhiyun .tristate = PMUX_TRI_##_tri, \ 41*4882a593Smuzhiyun .io = PMUX_PIN_##_io, \ 42*4882a593Smuzhiyun .lock = PMUX_PIN_LOCK_##_lock, \ 43*4882a593Smuzhiyun .od = PMUX_PIN_OD_DEFAULT, \ 44*4882a593Smuzhiyun .ioreset = PMUX_PIN_IO_RESET_##_ioreset \ 45*4882a593Smuzhiyun } 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \ 48*4882a593Smuzhiyun { \ 49*4882a593Smuzhiyun .drvgrp = PMUX_DRVGRP_##_drvgrp, \ 50*4882a593Smuzhiyun .slwf = _slwf, \ 51*4882a593Smuzhiyun .slwr = _slwr, \ 52*4882a593Smuzhiyun .drvup = _drvup, \ 53*4882a593Smuzhiyun .drvdn = _drvdn, \ 54*4882a593Smuzhiyun .lpmd = PMUX_LPMD_##_lpmd, \ 55*4882a593Smuzhiyun .schmt = PMUX_SCHMT_##_schmt, \ 56*4882a593Smuzhiyun .hsm = PMUX_HSM_##_hsm, \ 57*4882a593Smuzhiyun } 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun static struct pmux_pingrp_config tamonten_ng_pinmux_common[] = { 60*4882a593Smuzhiyun /* SDMMC1 pinmux */ 61*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT), 62*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT), 63*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT), 64*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT), 65*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT), 66*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT), 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* SDMMC3 pinmux */ 69*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT), 70*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT), 71*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT), 72*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT), 73*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT), 74*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT), 75*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT4_PD1, SDMMC3, UP, NORMAL, INPUT), 76*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT5_PD0, SDMMC3, UP, NORMAL, INPUT), 77*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT6_PD3, SDMMC3, UP, NORMAL, INPUT), 78*4882a593Smuzhiyun DEFAULT_PINMUX(SDMMC3_DAT7_PD4, SDMMC3, UP, NORMAL, INPUT), 79*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_IORDY_PI5, RSVD1, UP, NORMAL, INPUT), 80*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CS6_N_PI3, RSVD1, UP, NORMAL, INPUT), 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* SDMMC4 pinmux */ 83*4882a593Smuzhiyun LV_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 84*4882a593Smuzhiyun LV_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 85*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 86*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 87*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 88*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 89*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 90*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 91*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 92*4882a593Smuzhiyun LV_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DISABLE, DISABLE), 93*4882a593Smuzhiyun LV_PINMUX(SDMMC4_RST_N_PCC3, RSVD1, DOWN, NORMAL, INPUT, DISABLE, DISABLE), 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* I2C1 pinmux */ 96*4882a593Smuzhiyun I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 97*4882a593Smuzhiyun I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* I2C2 pinmux */ 100*4882a593Smuzhiyun I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 101*4882a593Smuzhiyun I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* I2C3 pinmux */ 104*4882a593Smuzhiyun I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 105*4882a593Smuzhiyun I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* I2C4 pinmux */ 108*4882a593Smuzhiyun I2C_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 109*4882a593Smuzhiyun I2C_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Power I2C pinmux */ 112*4882a593Smuzhiyun I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 113*4882a593Smuzhiyun I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE), 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* UART1 */ 116*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA0_PO1, UARTA, NORMAL, NORMAL, OUTPUT), 117*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA1_PO2, UARTA, NORMAL, NORMAL, INPUT), 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* UART2 */ 120*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_RXD_PC3, UARTB, NORMAL, NORMAL, INPUT), 121*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_TXD_PC2, UARTB, NORMAL, NORMAL, OUTPUT), 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun /* UART3 */ 124*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT), 125*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT), 126*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT), 127*4882a593Smuzhiyun DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT), 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* UART4 */ 130*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_CLK_PY0, UARTD, NORMAL, NORMAL, OUTPUT), 131*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DIR_PY1, UARTD, UP, NORMAL, INPUT), 132*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_NXT_PY2, UARTD, NORMAL, NORMAL, INPUT), 133*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_STP_PY3, UARTD, NORMAL, NORMAL, OUTPUT), 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun /* DAP */ 136*4882a593Smuzhiyun DEFAULT_PINMUX(CLK1_OUT_PW4, EXTPERIPH1, NORMAL, NORMAL, INPUT), 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun /* I2S1 */ 139*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT), 140*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT), 141*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT), 142*4882a593Smuzhiyun DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT), 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* SPDIF */ 145*4882a593Smuzhiyun DEFAULT_PINMUX(SPDIF_IN_PK6, SPDIF, NORMAL, NORMAL, INPUT), 146*4882a593Smuzhiyun DEFAULT_PINMUX(SPDIF_OUT_PK5, SPDIF, NORMAL, NORMAL, OUTPUT), 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* I2S2 */ 149*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, INPUT), 150*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, INPUT), 151*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, NORMAL, NORMAL, INPUT), 152*4882a593Smuzhiyun DEFAULT_PINMUX(DAP3_SCLK_PP3, I2S2, NORMAL, NORMAL, INPUT), 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* DAP4 */ 155*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT), 156*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT), 157*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT), 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun /* Tamonten GPIO */ 160*4882a593Smuzhiyun DEFAULT_PINMUX(PV2, RSVD1, NORMAL, NORMAL, OUTPUT), 161*4882a593Smuzhiyun DEFAULT_PINMUX(PV3, RSVD1, NORMAL, NORMAL, INPUT), 162*4882a593Smuzhiyun DEFAULT_PINMUX(SPI2_CS1_N_PW2, RSVD1, NORMAL, NORMAL, INPUT), 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /* LCD */ 165*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PWR1_PC1, DISPLAYA, NORMAL, NORMAL, INPUT), 166*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PWR2_PC6, DISPLAYA, NORMAL, NORMAL, INPUT), 167*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_SDIN_PZ2, DISPLAYA, NORMAL, NORMAL, INPUT), 168*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_SDOUT_PN5, DISPLAYA, NORMAL, NORMAL, INPUT), 169*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_WR_N_PZ3, DISPLAYA, NORMAL, NORMAL, INPUT), 170*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_CS0_N_PN4, DISPLAYA, NORMAL, NORMAL, INPUT), 171*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_DC0_PN6, DISPLAYA, NORMAL, NORMAL, INPUT), 172*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_SCK_PZ4, DISPLAYA, NORMAL, NORMAL, INPUT), 173*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PWR0_PB2, DISPLAYA, NORMAL, NORMAL, INPUT), 174*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_PCLK_PB3, DISPLAYA, NORMAL, NORMAL, INPUT), 175*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_DE_PJ1, DISPLAYA, NORMAL, NORMAL, INPUT), 176*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_HSYNC_PJ3, DISPLAYA, NORMAL, NORMAL, INPUT), 177*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_VSYNC_PJ4, DISPLAYA, NORMAL, NORMAL, INPUT), 178*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D0_PE0, DISPLAYA, NORMAL, NORMAL, INPUT), 179*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D1_PE1, DISPLAYA, NORMAL, NORMAL, INPUT), 180*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D2_PE2, DISPLAYA, NORMAL, NORMAL, INPUT), 181*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D3_PE3, DISPLAYA, NORMAL, NORMAL, INPUT), 182*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D4_PE4, DISPLAYA, NORMAL, NORMAL, INPUT), 183*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D5_PE5, DISPLAYA, NORMAL, NORMAL, INPUT), 184*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D6_PE6, DISPLAYA, NORMAL, NORMAL, INPUT), 185*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D7_PE7, DISPLAYA, NORMAL, NORMAL, INPUT), 186*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D8_PF0, DISPLAYA, NORMAL, NORMAL, INPUT), 187*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D9_PF1, DISPLAYA, NORMAL, NORMAL, INPUT), 188*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D10_PF2, DISPLAYA, NORMAL, NORMAL, INPUT), 189*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D11_PF3, DISPLAYA, NORMAL, NORMAL, INPUT), 190*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D12_PF4, DISPLAYA, NORMAL, NORMAL, INPUT), 191*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D13_PF5, DISPLAYA, NORMAL, NORMAL, INPUT), 192*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D14_PF6, DISPLAYA, NORMAL, NORMAL, INPUT), 193*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D15_PF7, DISPLAYA, NORMAL, NORMAL, INPUT), 194*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D16_PM0, DISPLAYA, NORMAL, NORMAL, INPUT), 195*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D17_PM1, DISPLAYA, NORMAL, NORMAL, INPUT), 196*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D18_PM2, DISPLAYA, NORMAL, NORMAL, INPUT), 197*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D19_PM3, DISPLAYA, NORMAL, NORMAL, INPUT), 198*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D20_PM4, DISPLAYA, NORMAL, NORMAL, INPUT), 199*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D21_PM5, DISPLAYA, NORMAL, NORMAL, INPUT), 200*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D22_PM6, DISPLAYA, NORMAL, NORMAL, INPUT), 201*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_D23_PM7, DISPLAYA, NORMAL, NORMAL, INPUT), 202*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_CS1_N_PW0, DISPLAYA, NORMAL, NORMAL, INPUT), 203*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_M1_PW1, DISPLAYA, NORMAL, NORMAL, INPUT), 204*4882a593Smuzhiyun DEFAULT_PINMUX(LCD_DC1_PD2, DISPLAYA, NORMAL, NORMAL, INPUT), 205*4882a593Smuzhiyun DEFAULT_PINMUX(CRT_HSYNC_PV6, CRT, NORMAL, NORMAL, OUTPUT), 206*4882a593Smuzhiyun DEFAULT_PINMUX(CRT_VSYNC_PV7, CRT, NORMAL, NORMAL, OUTPUT), 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun /* BT656 */ 209*4882a593Smuzhiyun LV_PINMUX(VI_MCLK_PT1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 210*4882a593Smuzhiyun LV_PINMUX(VI_PCLK_PT0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 211*4882a593Smuzhiyun LV_PINMUX(VI_HSYNC_PD7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 212*4882a593Smuzhiyun LV_PINMUX(VI_VSYNC_PD6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 213*4882a593Smuzhiyun LV_PINMUX(VI_D2_PL0, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 214*4882a593Smuzhiyun LV_PINMUX(VI_D3_PL1, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 215*4882a593Smuzhiyun LV_PINMUX(VI_D4_PL2, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 216*4882a593Smuzhiyun LV_PINMUX(VI_D5_PL3, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 217*4882a593Smuzhiyun LV_PINMUX(VI_D6_PL4, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 218*4882a593Smuzhiyun LV_PINMUX(VI_D7_PL5, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 219*4882a593Smuzhiyun LV_PINMUX(VI_D8_PL6, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 220*4882a593Smuzhiyun LV_PINMUX(VI_D9_PL7, VI, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 221*4882a593Smuzhiyun LV_PINMUX(VI_D11_PT3, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* GPIOs */ 224*4882a593Smuzhiyun DEFAULT_PINMUX(PU5, RSVD1, NORMAL, NORMAL, INPUT), 225*4882a593Smuzhiyun DEFAULT_PINMUX(PU6, RSVD1, NORMAL, NORMAL, INPUT), 226*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD12_PH4, RSVD1, NORMAL, NORMAL, INPUT), 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* LCD BL */ 229*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD8_PH0, PWM0, NORMAL, NORMAL, OUTPUT), 230*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD10_PH2, RSVD4, NORMAL, NORMAL, OUTPUT), 231*4882a593Smuzhiyun 232*4882a593Smuzhiyun /* SPI4 */ 233*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A16_PJ7, SPI4, NORMAL, NORMAL, INPUT), 234*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A17_PB0, SPI4, NORMAL, NORMAL, INPUT), 235*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A18_PB1, SPI4, NORMAL, NORMAL, INPUT), 236*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_A19_PK7, SPI4, NORMAL, NORMAL, INPUT), 237*4882a593Smuzhiyun 238*4882a593Smuzhiyun /* Video input GPIO */ 239*4882a593Smuzhiyun DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, NORMAL, INPUT), 240*4882a593Smuzhiyun DEFAULT_PINMUX(PBB0, RSVD1, NORMAL, NORMAL, INPUT), 241*4882a593Smuzhiyun DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, NORMAL, INPUT), 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun /* Sensor GPIO */ 244*4882a593Smuzhiyun DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, NORMAL, INPUT), 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun /* JTAG */ 247*4882a593Smuzhiyun DEFAULT_PINMUX(JTAG_RTCK_PU7, RTCK, NORMAL, NORMAL, OUTPUT), 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* Power controls */ 250*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CS2_N_PK3, RSVD1, NORMAL, NORMAL, INPUT), 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun /* SPI1 */ 253*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_MOSI_PX4, SPI1, NORMAL, NORMAL, INPUT), 254*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_SCK_PX5, SPI1, NORMAL, NORMAL, INPUT), 255*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_CS0_N_PX6, SPI1, NORMAL, NORMAL, INPUT), 256*4882a593Smuzhiyun DEFAULT_PINMUX(SPI1_MISO_PX7, SPI1, NORMAL, NORMAL, INPUT), 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun /* PMU */ 259*4882a593Smuzhiyun DEFAULT_PINMUX(PV0, RSVD1, UP, NORMAL, INPUT), 260*4882a593Smuzhiyun DEFAULT_PINMUX(SYS_CLK_REQ_PZ5, SYSCLK, NORMAL, NORMAL, OUTPUT), 261*4882a593Smuzhiyun DEFAULT_PINMUX(CLK_32K_IN, SYSCLK, NORMAL, NORMAL, INPUT), 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun /* PCI */ 264*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L0_PRSNT_N_PDD0, PCIE, NORMAL, NORMAL, INPUT), 265*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L0_RST_N_PDD1, PCIE, NORMAL, NORMAL, OUTPUT), 266*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L0_CLKREQ_N_PDD2, PCIE, NORMAL, NORMAL, INPUT), 267*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_WAKE_N_PDD3, PCIE, NORMAL, NORMAL, INPUT), 268*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L1_PRSNT_N_PDD4, PCIE, NORMAL, NORMAL, INPUT), 269*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L1_RST_N_PDD5, PCIE, NORMAL, NORMAL, OUTPUT), 270*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L1_CLKREQ_N_PDD6, PCIE, NORMAL, NORMAL, INPUT), 271*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L2_PRSNT_N_PDD7, PCIE, NORMAL, NORMAL, INPUT), 272*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L2_RST_N_PCC6, PCIE, NORMAL, NORMAL, OUTPUT), 273*4882a593Smuzhiyun DEFAULT_PINMUX(PEX_L2_CLKREQ_N_PCC7, PCIE, NORMAL, NORMAL, INPUT), 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* HDMI */ 276*4882a593Smuzhiyun DEFAULT_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT), 277*4882a593Smuzhiyun DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, NORMAL, TRISTATE, INPUT), 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun static struct pmux_pingrp_config unused_pins_lowpower[] = { 281*4882a593Smuzhiyun /* UART1 - NC */ 282*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA2_PO3, UARTA, NORMAL, NORMAL, INPUT), 283*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA3_PO4, UARTA, NORMAL, NORMAL, INPUT), 284*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA4_PO5, UARTA, NORMAL, NORMAL, INPUT), 285*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA5_PO6, UARTA, NORMAL, NORMAL, INPUT), 286*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA6_PO7, UARTA, NORMAL, NORMAL, INPUT), 287*4882a593Smuzhiyun DEFAULT_PINMUX(ULPI_DATA7_PO0, UARTA, NORMAL, NORMAL, INPUT), 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun /* UART2 - NC */ 290*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, INPUT), 291*4882a593Smuzhiyun DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT), 292*4882a593Smuzhiyun 293*4882a593Smuzhiyun /* DAP - NC */ 294*4882a593Smuzhiyun DEFAULT_PINMUX(CLK1_REQ_PEE2, RSVD1, NORMAL, NORMAL, INPUT), 295*4882a593Smuzhiyun DEFAULT_PINMUX(CLK3_OUT_PEE0, RSVD1, NORMAL, NORMAL, INPUT), 296*4882a593Smuzhiyun DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, NORMAL, INPUT), 297*4882a593Smuzhiyun 298*4882a593Smuzhiyun /* DAP4 - NC */ 299*4882a593Smuzhiyun DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT), 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* Tamonten GPIO - NC */ 302*4882a593Smuzhiyun DEFAULT_PINMUX(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, INPUT), 303*4882a593Smuzhiyun DEFAULT_PINMUX(CLK2_REQ_PCC5, DAP, NORMAL, NORMAL, INPUT), 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun /* BT656 - NC */ 306*4882a593Smuzhiyun LV_PINMUX(VI_D0_PT4, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 307*4882a593Smuzhiyun LV_PINMUX(VI_D1_PD5, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 308*4882a593Smuzhiyun LV_PINMUX(VI_D10_PT2, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE), 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* GPIO - NC */ 311*4882a593Smuzhiyun DEFAULT_PINMUX(PU0, RSVD1, NORMAL, NORMAL, INPUT), 312*4882a593Smuzhiyun DEFAULT_PINMUX(PU1, RSVD1, NORMAL, NORMAL, INPUT), 313*4882a593Smuzhiyun DEFAULT_PINMUX(PU2, RSVD1, NORMAL, NORMAL, INPUT), 314*4882a593Smuzhiyun DEFAULT_PINMUX(PU3, RSVD1, NORMAL, NORMAL, INPUT), 315*4882a593Smuzhiyun DEFAULT_PINMUX(PU4, RSVD1, NORMAL, NORMAL, INPUT), 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun /* Video input - NC */ 318*4882a593Smuzhiyun DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, NORMAL, INPUT), 319*4882a593Smuzhiyun DEFAULT_PINMUX(PBB3, RSVD1, NORMAL, NORMAL, INPUT), 320*4882a593Smuzhiyun DEFAULT_PINMUX(PBB5, RSVD1, NORMAL, NORMAL, INPUT), 321*4882a593Smuzhiyun DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, NORMAL, INPUT), 322*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW11_PS3, RSVD1, NORMAL, NORMAL, INPUT), 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun /* KBC keys - NC */ 325*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT), 326*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT), 327*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW2_PR2, KBC, UP, NORMAL, INPUT), 328*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW3_PR3, KBC, UP, NORMAL, INPUT), 329*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW4_PR4, KBC, UP, NORMAL, INPUT), 330*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW5_PR5, KBC, UP, NORMAL, INPUT), 331*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW6_PR6, KBC, UP, NORMAL, INPUT), 332*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW7_PR7, KBC, UP, NORMAL, INPUT), 333*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT), 334*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW9_PS1, KBC, UP, NORMAL, INPUT), 335*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW10_PS2, KBC, UP, NORMAL, INPUT), 336*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW12_PS4, KBC, UP, NORMAL, INPUT), 337*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW13_PS5, KBC, UP, NORMAL, INPUT), 338*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW14_PS6, KBC, UP, NORMAL, INPUT), 339*4882a593Smuzhiyun DEFAULT_PINMUX(KB_ROW15_PS7, KBC, UP, NORMAL, INPUT), 340*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT), 341*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT), 342*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT), 343*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, INPUT), 344*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL4_PQ4, KBC, UP, NORMAL, INPUT), 345*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL5_PQ5, KBC, UP, NORMAL, INPUT), 346*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, INPUT), 347*4882a593Smuzhiyun DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, INPUT), 348*4882a593Smuzhiyun 349*4882a593Smuzhiyun /* PMU - NC */ 350*4882a593Smuzhiyun DEFAULT_PINMUX(CLK_32K_OUT_PA0, RSVD1, NORMAL, NORMAL, INPUT), 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun /* Power rails GPIO - NC */ 353*4882a593Smuzhiyun DEFAULT_PINMUX(SPI2_SCK_PX2, RSVD1, NORMAL, NORMAL, INPUT), 354*4882a593Smuzhiyun DEFAULT_PINMUX(PBB4, RSVD1, NORMAL, NORMAL, INPUT), 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun /* Others - NC */ 357*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_WP_N_PC7, RSVD1, NORMAL, NORMAL, INPUT), 358*4882a593Smuzhiyun DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT), 359*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_WAIT_PI7, NAND, UP, TRISTATE, OUTPUT), 360*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_ADV_N_PK0, NAND, NORMAL, TRISTATE, OUTPUT), 361*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CLK_PK1, NAND, NORMAL, TRISTATE, OUTPUT), 362*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CS3_N_PK4, NAND, NORMAL, NORMAL, OUTPUT), 363*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_CS7_N_PI6, NAND, UP, NORMAL, INPUT), 364*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD0_PG0, NAND, NORMAL, TRISTATE, OUTPUT), 365*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD1_PG1, NAND, NORMAL, TRISTATE, OUTPUT), 366*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD2_PG2, NAND, NORMAL, TRISTATE, OUTPUT), 367*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD3_PG3, NAND, NORMAL, TRISTATE, OUTPUT), 368*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD4_PG4, NAND, NORMAL, TRISTATE, OUTPUT), 369*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD5_PG5, NAND, NORMAL, TRISTATE, OUTPUT), 370*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD6_PG6, NAND, NORMAL, TRISTATE, OUTPUT), 371*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD7_PG7, NAND, NORMAL, TRISTATE, OUTPUT), 372*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD9_PH1, PWM1, NORMAL, NORMAL, OUTPUT), 373*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD11_PH3, NAND, NORMAL, NORMAL, OUTPUT), 374*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_AD13_PH5, NAND, UP, NORMAL, INPUT), 375*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_WR_N_PI0, NAND, NORMAL, TRISTATE, OUTPUT), 376*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_OE_N_PI1, NAND, NORMAL, TRISTATE, OUTPUT), 377*4882a593Smuzhiyun DEFAULT_PINMUX(GMI_DQS_PI2, NAND, NORMAL, TRISTATE, OUTPUT), 378*4882a593Smuzhiyun }; 379*4882a593Smuzhiyun 380*4882a593Smuzhiyun static struct pmux_drvgrp_config tamonten_ng_padctrl[] = { 381*4882a593Smuzhiyun /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */ 382*4882a593Smuzhiyun DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR, 383*4882a593Smuzhiyun SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE), 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun #endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */ 386