1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2007-2008 3*4882a593Smuzhiyun * Stelian Pop <stelian@popies.net> 4*4882a593Smuzhiyun * Lead Tech Design <www.leadtechdesign.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <common.h> 10*4882a593Smuzhiyun #include <debug_uart.h> 11*4882a593Smuzhiyun #include <asm/io.h> 12*4882a593Smuzhiyun #include <asm/arch/at91sam9260_matrix.h> 13*4882a593Smuzhiyun #include <asm/arch/at91sam9_smc.h> 14*4882a593Smuzhiyun #include <asm/arch/at91_common.h> 15*4882a593Smuzhiyun #include <asm/arch/clk.h> 16*4882a593Smuzhiyun #include <asm/arch/gpio.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* ------------------------------------------------------------------------- */ 21*4882a593Smuzhiyun /* 22*4882a593Smuzhiyun * Miscelaneous platform dependent initialisations 23*4882a593Smuzhiyun */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND at91sam9260ek_nand_hw_init(void)26*4882a593Smuzhiyunstatic void at91sam9260ek_nand_hw_init(void) 27*4882a593Smuzhiyun { 28*4882a593Smuzhiyun struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC; 29*4882a593Smuzhiyun struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX; 30*4882a593Smuzhiyun unsigned long csa; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Assign CS3 to NAND/SmartMedia Interface */ 33*4882a593Smuzhiyun csa = readl(&matrix->ebicsa); 34*4882a593Smuzhiyun csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA; 35*4882a593Smuzhiyun writel(csa, &matrix->ebicsa); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* Configure SMC CS3 for NAND/SmartMedia */ 38*4882a593Smuzhiyun writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) | 39*4882a593Smuzhiyun AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0), 40*4882a593Smuzhiyun &smc->cs[3].setup); 41*4882a593Smuzhiyun writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) | 42*4882a593Smuzhiyun AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3), 43*4882a593Smuzhiyun &smc->cs[3].pulse); 44*4882a593Smuzhiyun writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), 45*4882a593Smuzhiyun &smc->cs[3].cycle); 46*4882a593Smuzhiyun writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | 47*4882a593Smuzhiyun AT91_SMC_MODE_EXNW_DISABLE | 48*4882a593Smuzhiyun #ifdef CONFIG_SYS_NAND_DBW_16 49*4882a593Smuzhiyun AT91_SMC_MODE_DBW_16 | 50*4882a593Smuzhiyun #else /* CONFIG_SYS_NAND_DBW_8 */ 51*4882a593Smuzhiyun AT91_SMC_MODE_DBW_8 | 52*4882a593Smuzhiyun #endif 53*4882a593Smuzhiyun AT91_SMC_MODE_TDF_CYCLE(2), 54*4882a593Smuzhiyun &smc->cs[3].mode); 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Configure RDY/BSY */ 57*4882a593Smuzhiyun at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1); 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* Enable NandFlash */ 60*4882a593Smuzhiyun at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1); 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun } 63*4882a593Smuzhiyun #endif 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART_BOARD_INIT board_debug_uart_init(void)66*4882a593Smuzhiyunvoid board_debug_uart_init(void) 67*4882a593Smuzhiyun { 68*4882a593Smuzhiyun at91_seriald_hw_init(); 69*4882a593Smuzhiyun } 70*4882a593Smuzhiyun #endif 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #ifdef CONFIG_BOARD_EARLY_INIT_F board_early_init_f(void)73*4882a593Smuzhiyunint board_early_init_f(void) 74*4882a593Smuzhiyun { 75*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_UART 76*4882a593Smuzhiyun debug_uart_init(); 77*4882a593Smuzhiyun #endif 78*4882a593Smuzhiyun return 0; 79*4882a593Smuzhiyun } 80*4882a593Smuzhiyun #endif 81*4882a593Smuzhiyun board_init(void)82*4882a593Smuzhiyunint board_init(void) 83*4882a593Smuzhiyun { 84*4882a593Smuzhiyun /* adress of boot parameters */ 85*4882a593Smuzhiyun gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #ifdef CONFIG_CMD_NAND 88*4882a593Smuzhiyun at91sam9260ek_nand_hw_init(); 89*4882a593Smuzhiyun #endif 90*4882a593Smuzhiyun return 0; 91*4882a593Smuzhiyun } 92*4882a593Smuzhiyun dram_init(void)93*4882a593Smuzhiyunint dram_init(void) 94*4882a593Smuzhiyun { 95*4882a593Smuzhiyun gd->ram_size = get_ram_size( 96*4882a593Smuzhiyun (void *)CONFIG_SYS_SDRAM_BASE, 97*4882a593Smuzhiyun CONFIG_SYS_SDRAM_SIZE); 98*4882a593Smuzhiyun return 0; 99*4882a593Smuzhiyun } 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #ifdef CONFIG_RESET_PHY_R reset_phy(void)102*4882a593Smuzhiyunvoid reset_phy(void) 103*4882a593Smuzhiyun { 104*4882a593Smuzhiyun } 105*4882a593Smuzhiyun #endif 106