1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * (C) Copyright 2011 3*4882a593Smuzhiyun * Linaro 4*4882a593Smuzhiyun * Linus Walleij <linus.walleij@linaro.org> 5*4882a593Smuzhiyun * Register definitions for the System Controller (SC) and 6*4882a593Smuzhiyun * the similar "CP Controller" found in the ARM Integrator/AP and 7*4882a593Smuzhiyun * Integrator/CP reference designs 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __ARM_SC_H 13*4882a593Smuzhiyun #define __ARM_SC_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define SC_BASE 0x11000000 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * The system controller registers 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define SC_ID_OFFSET 0x00 21*4882a593Smuzhiyun #define SC_OSC_OFFSET 0x04 22*4882a593Smuzhiyun /* Setting this bit switches to 25 MHz mode, clear means 33 MHz */ 23*4882a593Smuzhiyun #define SC_OSC_DIVXY (1 << 8) 24*4882a593Smuzhiyun #define SC_CTRLS_OFFSET 0x08 25*4882a593Smuzhiyun #define SC_CTRLC_OFFSET 0x0C 26*4882a593Smuzhiyun /* Set bits by writing CTRLS, clear bits by writing CTRLC */ 27*4882a593Smuzhiyun #define SC_CTRL_SOFTRESET (1 << 0) 28*4882a593Smuzhiyun #define SC_CTRL_FLASHVPP (1 << 1) 29*4882a593Smuzhiyun #define SC_CTRL_FLASHWP (1 << 2) 30*4882a593Smuzhiyun #define SC_CTRL_UART1DTR (1 << 4) 31*4882a593Smuzhiyun #define SC_CTRL_UART1RTS (1 << 5) 32*4882a593Smuzhiyun #define SC_CTRL_UART0DTR (1 << 6) 33*4882a593Smuzhiyun #define SC_CTRL_UART0RTS (1 << 7) 34*4882a593Smuzhiyun #define SC_DEC_OFFSET 0x10 35*4882a593Smuzhiyun #define SC_ARB_OFFSET 0x14 36*4882a593Smuzhiyun #define SC_PCI_OFFSET 0x18 37*4882a593Smuzhiyun #define SC_PCI_PCIEN (1 << 0) 38*4882a593Smuzhiyun #define SC_PCI_PCIBINT_CLR (1 << 1) 39*4882a593Smuzhiyun #define SC_LOCK_OFFSET 0x1C 40*4882a593Smuzhiyun #define SC_LBFADDR_OFFSET 0x20 41*4882a593Smuzhiyun #define SC_LBFCODE_OFFSET 0x24 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define SC_ID (SC_BASE + SC_ID_OFFSET) 44*4882a593Smuzhiyun #define SC_OSC (SC_BASE + SC_OSC_OFFSET) 45*4882a593Smuzhiyun #define SC_CTRLS (SC_BASE + SC_CTRLS_OFFSET) 46*4882a593Smuzhiyun #define SC_CTRLC (SC_BASE + SC_CTRLC_OFFSET) 47*4882a593Smuzhiyun #define SC_DEC (SC_BASE + SC_DEC_OFFSET) 48*4882a593Smuzhiyun #define SC_ARB (SC_BASE + SC_ARB_OFFSET) 49*4882a593Smuzhiyun #define SC_PCI (SC_BASE + SC_PCI_OFFSET) 50*4882a593Smuzhiyun #define SC_LOCK (SC_BASE + SC_LOCK_OFFSET) 51*4882a593Smuzhiyun #define SC_LBFADDR (SC_BASE + SC_LBFADDR_OFFSET) 52*4882a593Smuzhiyun #define SC_LBFCODE (SC_BASE + SC_LBFCODE_OFFSET) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* 55*4882a593Smuzhiyun * The Integrator/CP as a smaller set of registers, at a different 56*4882a593Smuzhiyun * offset - probably not to disturb old software. 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define CP_BASE 0xCB000000 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define CP_IDFIELD_OFFSET 0x00 62*4882a593Smuzhiyun #define CP_FLASHPROG_OFFSET 0x04 63*4882a593Smuzhiyun #define CP_FLASHPROG_FLVPPEN (1 << 0) 64*4882a593Smuzhiyun #define CP_FLASHPROG_FLWREN (1 << 1) 65*4882a593Smuzhiyun #define CP_FLASHPROG_FLASHSIZE (1 << 2) 66*4882a593Smuzhiyun #define CP_FLASHPROG_EXTRABANK (1 << 3) 67*4882a593Smuzhiyun #define CP_INTREG_OFFSET 0x08 68*4882a593Smuzhiyun #define CP_DECODE_OFFSET 0x0C 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define CP_IDFIELD (CP_BASE + CP_ID_OFFSET) 71*4882a593Smuzhiyun #define CP_FLASHPROG (CP_BASE + CP_FLASHPROG_OFFSET) 72*4882a593Smuzhiyun #define CP_INTREG (CP_BASE + CP_INTREG_OFFSET) 73*4882a593Smuzhiyun #define CP_DECODE (CP_BASE + CP_DECODE_OFFSET) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif 76