1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2017 Armadeus Systems
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun #include <asm/arch/clock.h>
8*4882a593Smuzhiyun #include <asm/arch/mx6-pins.h>
9*4882a593Smuzhiyun #include <asm/arch/opos6ul.h>
10*4882a593Smuzhiyun #include <asm/arch/sys_proto.h>
11*4882a593Smuzhiyun #include <asm/gpio.h>
12*4882a593Smuzhiyun #include <asm/mach-imx/iomux-v3.h>
13*4882a593Smuzhiyun #include <asm/io.h>
14*4882a593Smuzhiyun #include <common.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun DECLARE_GLOBAL_DATA_PTR;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_MXS
19*4882a593Smuzhiyun #define LCD_PAD_CTRL ( \
20*4882a593Smuzhiyun PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
21*4882a593Smuzhiyun PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm \
22*4882a593Smuzhiyun )
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun static iomux_v3_cfg_t const lcd_pads[] = {
25*4882a593Smuzhiyun MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
26*4882a593Smuzhiyun MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
27*4882a593Smuzhiyun MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
28*4882a593Smuzhiyun MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
29*4882a593Smuzhiyun MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
30*4882a593Smuzhiyun MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
31*4882a593Smuzhiyun MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
32*4882a593Smuzhiyun MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
33*4882a593Smuzhiyun MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
34*4882a593Smuzhiyun MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
35*4882a593Smuzhiyun MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
36*4882a593Smuzhiyun MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
37*4882a593Smuzhiyun MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
38*4882a593Smuzhiyun MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
39*4882a593Smuzhiyun MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
40*4882a593Smuzhiyun MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
41*4882a593Smuzhiyun MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
42*4882a593Smuzhiyun MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
43*4882a593Smuzhiyun MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
44*4882a593Smuzhiyun MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
45*4882a593Smuzhiyun MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
46*4882a593Smuzhiyun MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun
setup_lcd(void)51*4882a593Smuzhiyun int setup_lcd(void)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct gpio_desc backlight;
54*4882a593Smuzhiyun int ret;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun enable_lcdif_clock(LCDIF1_BASE_ADDR, 1);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* Set Brightness to high */
61*4882a593Smuzhiyun ret = dm_gpio_lookup_name("GPIO4_10", &backlight);
62*4882a593Smuzhiyun if (ret) {
63*4882a593Smuzhiyun printf("Cannot get GPIO4_10\n");
64*4882a593Smuzhiyun return ret;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun ret = dm_gpio_request(&backlight, "backlight");
68*4882a593Smuzhiyun if (ret) {
69*4882a593Smuzhiyun printf("Cannot request GPIO4_10\n");
70*4882a593Smuzhiyun return ret;
71*4882a593Smuzhiyun }
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun dm_gpio_set_dir_flags(&backlight, GPIOD_IS_OUT);
74*4882a593Smuzhiyun dm_gpio_set_value(&backlight, 1);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun return 0;
77*4882a593Smuzhiyun }
78*4882a593Smuzhiyun #endif
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun #ifdef CONFIG_USB_EHCI_MX6
81*4882a593Smuzhiyun #define USB_OTHERREGS_OFFSET 0x800
82*4882a593Smuzhiyun #define UCTRL_PWR_POL (1 << 9)
83*4882a593Smuzhiyun
board_ehci_hcd_init(int port)84*4882a593Smuzhiyun int board_ehci_hcd_init(int port)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun u32 *usbnc_usb_ctrl;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun if (port > 1)
89*4882a593Smuzhiyun return -EINVAL;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
92*4882a593Smuzhiyun port * 4);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /* Set Power polarity */
95*4882a593Smuzhiyun setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return 0;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun #endif
100*4882a593Smuzhiyun
opos6ul_board_late_init(void)101*4882a593Smuzhiyun int opos6ul_board_late_init(void)
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun #ifdef CONFIG_VIDEO_MXS
104*4882a593Smuzhiyun setup_lcd();
105*4882a593Smuzhiyun #endif
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun return 0;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun #ifdef CONFIG_SPL_BUILD
111*4882a593Smuzhiyun #define UART_PAD_CTRL ( \
112*4882a593Smuzhiyun PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
113*4882a593Smuzhiyun PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST \
114*4882a593Smuzhiyun )
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun static iomux_v3_cfg_t const uart1_pads[] = {
117*4882a593Smuzhiyun MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
118*4882a593Smuzhiyun MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
opos6ul_setup_uart_debug(void)121*4882a593Smuzhiyun void opos6ul_setup_uart_debug(void)
122*4882a593Smuzhiyun {
123*4882a593Smuzhiyun imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun #endif /* CONFIG_SPL_BUILD */
126