1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr> 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include <config.h> 8*4882a593Smuzhiyun#include <generated/asm-offsets.h> 9*4882a593Smuzhiyun#include <asm/macro.h> 10*4882a593Smuzhiyun#include <asm/arch/imx-regs.h> 11*4882a593Smuzhiyun#include "apf27.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun .macro init_aipi 14*4882a593Smuzhiyun /* 15*4882a593Smuzhiyun * setup AIPI1 and AIPI2 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL 18*4882a593Smuzhiyun write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL 19*4882a593Smuzhiyun write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL 20*4882a593Smuzhiyun write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Change SDRAM signal strengh */ 23*4882a593Smuzhiyun ldr r0, =GPCR 24*4882a593Smuzhiyun ldr r1, =ACFG_GPCR_VAL 25*4882a593Smuzhiyun ldr r5, [r0] 26*4882a593Smuzhiyun orr r5, r5, r1 27*4882a593Smuzhiyun str r5, [r0] 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun .endm /* init_aipi */ 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun .macro init_clock 32*4882a593Smuzhiyun ldr r0, =CSCR 33*4882a593Smuzhiyun /* disable MPLL/SPLL first */ 34*4882a593Smuzhiyun ldr r1, [r0] 35*4882a593Smuzhiyun bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) 36*4882a593Smuzhiyun str r1, [r0] 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* 39*4882a593Smuzhiyun * pll clock initialization predefined in apf27.h 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun write32 MPCTL0, ACFG_MPCTL0_VAL 42*4882a593Smuzhiyun write32 SPCTL0, ACFG_SPCTL0_VAL 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * add some delay here 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun mov r1, #0x1000 50*4882a593Smuzhiyun 1: subs r1, r1, #0x1 51*4882a593Smuzhiyun bne 1b 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* peripheral clock divider */ 54*4882a593Smuzhiyun write32 PCDR0, ACFG_PCDR0_VAL 55*4882a593Smuzhiyun write32 PCDR1, ACFG_PCDR1_VAL 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Configure PCCR0 and PCCR1 */ 58*4882a593Smuzhiyun write32 PCCR0, ACFG_PCCR0_VAL 59*4882a593Smuzhiyun write32 PCCR1, ACFG_PCCR1_VAL 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun .endm /* init_clock */ 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun .macro init_ddr 64*4882a593Smuzhiyun /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ 65*4882a593Smuzhiyun ldr r0, =IMX_ESD_BASE 66*4882a593Smuzhiyun ldr r4, =ESDMISC_SDRAM_RDY 67*4882a593Smuzhiyun2: ldr r1, [r0, #ESDMISC_ROF] 68*4882a593Smuzhiyun ands r1, r1, r4 69*4882a593Smuzhiyun bpl 2b 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ 72*4882a593Smuzhiyun ldr r0, =IMX_ESD_BASE 73*4882a593Smuzhiyun ldr r4, =ACFG_ESDMISC_VAL 74*4882a593Smuzhiyun orr r1, r4, #ESDMISC_MDDR_DL_RST 75*4882a593Smuzhiyun str r1, [r0, #ESDMISC_ROF] 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Hold for more than 200ns */ 78*4882a593Smuzhiyun ldr r1, =0x10000 79*4882a593Smuzhiyun1: subs r1, r1, #0x1 80*4882a593Smuzhiyun bne 1b 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun str r4, [r0] 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun ldr r0, =IMX_ESD_BASE 85*4882a593Smuzhiyun ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL 86*4882a593Smuzhiyun str r1, [r0, #ESDCFG0_ROF] 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun ldr r0, =IMX_ESD_BASE 89*4882a593Smuzhiyun ldr r1, =ACFG_PRECHARGE_CMD 90*4882a593Smuzhiyun str r1, [r0, #ESDCTL0_ROF] 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* write8(0xA0001000, any value) */ 93*4882a593Smuzhiyun ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL 94*4882a593Smuzhiyun strb r2, [r1] 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun ldr r1, =ACFG_AUTOREFRESH_CMD 97*4882a593Smuzhiyun str r1, [r0, #ESDCTL0_ROF] 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun ldr r6,=0x7 /* load loop counter */ 102*4882a593Smuzhiyun1: str r5,[r4] /* run auto-refresh cycle to array 0 */ 103*4882a593Smuzhiyun subs r6,r6,#1 104*4882a593Smuzhiyun bne 1b 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun ldr r1, =ACFG_SET_MODE_REG_CMD 107*4882a593Smuzhiyun str r1, [r0, #ESDCTL0_ROF] 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun /* set standard mode register */ 110*4882a593Smuzhiyun ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL 111*4882a593Smuzhiyun strb r2, [r4] 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* set extended mode register */ 114*4882a593Smuzhiyun ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL 115*4882a593Smuzhiyun strb r5, [r4] 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun ldr r1, =ACFG_NORMAL_RW_CMD 118*4882a593Smuzhiyun str r1, [r0, #ESDCTL0_ROF] 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /* 2nd sdram */ 121*4882a593Smuzhiyun ldr r0, =IMX_ESD_BASE 122*4882a593Smuzhiyun ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL 123*4882a593Smuzhiyun str r1, [r0, #ESDCFG1_ROF] 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun ldr r0, =IMX_ESD_BASE 126*4882a593Smuzhiyun ldr r1, =ACFG_PRECHARGE_CMD 127*4882a593Smuzhiyun str r1, [r0, #ESDCTL1_ROF] 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* write8(0xB0001000, any value) */ 130*4882a593Smuzhiyun ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL 131*4882a593Smuzhiyun strb r2, [r1] 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun ldr r1, =ACFG_AUTOREFRESH_CMD 134*4882a593Smuzhiyun str r1, [r0, #ESDCTL1_ROF] 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun ldr r6,=0x7 /* load loop counter */ 139*4882a593Smuzhiyun1: str r5,[r4] /* run auto-refresh cycle to array 0 */ 140*4882a593Smuzhiyun subs r6,r6,#1 141*4882a593Smuzhiyun bne 1b 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun ldr r1, =ACFG_SET_MODE_REG_CMD 144*4882a593Smuzhiyun str r1, [r0, #ESDCTL1_ROF] 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* set standard mode register */ 147*4882a593Smuzhiyun ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL 148*4882a593Smuzhiyun strb r2, [r4] 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun /* set extended mode register */ 151*4882a593Smuzhiyun ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL 152*4882a593Smuzhiyun strb r2, [r4] 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun ldr r1, =ACFG_NORMAL_RW_CMD 155*4882a593Smuzhiyun str r1, [r0, #ESDCTL1_ROF] 156*4882a593Smuzhiyun .endm /* init_ddr */ 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun.globl lowlevel_init 159*4882a593Smuzhiyunlowlevel_init: 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun init_aipi 162*4882a593Smuzhiyun init_clock 163*4882a593Smuzhiyun#ifdef CONFIG_SPL_BUILD 164*4882a593Smuzhiyun init_ddr 165*4882a593Smuzhiyun#endif 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun mov pc, lr 168