1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2013 Boundary Devices 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun/* ZQ Calibration */ 7*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 8*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 9*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 10*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F 11*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 12*4882a593Smuzhiyun/* 13*4882a593Smuzhiyun * DQS gating, read delay, write delay calibration values 14*4882a593Smuzhiyun */ 15*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217 16*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B 17*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B 18*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C 19*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C 20*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48 21*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40 22*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E 23*4882a593Smuzhiyun/* read data bit delay */ 24*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 25*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 26*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 27*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 28*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 29*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 30*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 31*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 32*4882a593Smuzhiyun/* Complete calibration by forced measurment */ 33*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 34*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 35*4882a593Smuzhiyun/* in DDR3, 64-bit mode, only MMDC0 is initiated */ 36*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDPDC, 0x00020025 37*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 38*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313 39*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63 40*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 41*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 42*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 43*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 44*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOR, 0x006B1023 45*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDASP, 0x00000027 46*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 47*4882a593Smuzhiyun 48*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 49*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 50*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 51*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 52*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun/* final ddr setup */ 55*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDREF, 0x00005800 56*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117 57*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117 58*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDPDC, 0x00025565 59*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MAPSR, 0x00011006 60*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 61