1*4882a593Smuzhiyun/* 2*4882a593Smuzhiyun * Copyright (C) 2013 Boundary Devices 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * SPDX-License-Identifier: GPL-2.0+ 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun/* ZQ Calibration */ 7*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 8*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 9*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F 10*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F 11*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F 12*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F 13*4882a593Smuzhiyun/* 14*4882a593Smuzhiyun * DQS gating, read delay, write delay calibration values 15*4882a593Smuzhiyun * based on calibration compare of 0x00ffff00 16*4882a593Smuzhiyun */ 17*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E 18*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200 19*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202 20*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172 21*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C 22*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49 23*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133 24*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E 25*4882a593Smuzhiyun/* read data bit delay */ 26*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 27*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 28*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 29*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 30*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 31*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 32*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 33*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 34*4882a593Smuzhiyun/* Complete calibration by forced measurment */ 35*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 36*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 37*4882a593Smuzhiyun/* in DDR3, 64-bit mode, only MMDC0 is initiated */ 38*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d 39*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 40*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323 41*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63 42*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db 43*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 44*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 45*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 46*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDOR, 0x00440e21 47*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDASP, 0x00000027 48*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 49*4882a593Smuzhiyun/* MR2 */ 50*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 51*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a 52*4882a593Smuzhiyun/* MR3 */ 53*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 54*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b 55*4882a593Smuzhiyun/* MR1 */ 56*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 57*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 58*4882a593Smuzhiyun/* MR0 */ 59*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x07208030 60*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x07208038 61*4882a593Smuzhiyun/* ZQ calibration */ 62*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 63*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 64*4882a593Smuzhiyun/* final ddr setup */ 65*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDREF, 0x00005800 66*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 67*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007 68*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d 69*4882a593SmuzhiyunDATA 4, MX6_MMDC_P1_MAPSR, 0x00011006 70*4882a593SmuzhiyunDATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 71